The WiFi-based localization approach has been widely used in the indoor environment. This paper proposes a MultIple Fingerprints-based Indoor localization system (MIFI). MIFI is based on the depthwise separable convolution neural network technique and utilizes Unmanned Aerial Vehicle (UAV) to help with transmitting fingerprint data. With the help of UAV, human effort can be decreased. In the training phase, we collect the Channel State Information (CSI) of the reference points. In the testing phase, CSI sent at the test locations are collected by Raspberry PI 4 as the input, then the system will output the predicted location. The experiment results show that MIFI can achieve a higher classification accuracy and mean localization distance error than the baseline work. Compared to the CSI data sent from UAV, only a minor performance is lost due to the drift problems of UAV.

The mapping of DNA subsequences to a known reference genome, referred to as “short-read mapping”, is essential for next-generation sequencing. Hundreds of millions of short reads need to be aligned to a tremendously long reference sequence, making short-read mapping very time consuming. In this article, a high-throughput hardware accelerator is proposed so as to accelerate this task. A Bloom filter-based candidate mapping location (CML) generator and a folded processing element (PE) array are proposed to address CML selection and the Smith-Waterman (SW) alignment algorithm, respectively. It is shown that the proposed CML generator reduces the required memory access by 40 percent by employing a down-sampling scheme when compared to the Ferragina-Manzini index (FM-index) solution. The proposed hierarchical Bloom filter (HBF) that includes optimized parameters achieves a 1.5×104times acceleration over the conventional Bloom filter. The proposed memory re-allocation scheme further reduces the memory access time for the HBF by a factor of 256. The proposed folded PE array delivers a 1.2-to-3.2 times higher giga cell updates per second (GCUPS). The processing time can be further reduced by 53-to-72 percent by employing a fully pipelined PE array that allows for a tailored shift amount for seeding. The accelerator is realized on a Stratix V GX FPGA with 16GB external SDRAM. Operated at 200MHz, the proposed FPGA accelerator delivers a 2.1-to-11 times higher throughput with the highest 99 percent accuracy and 98 percent sensitivity compared to the state-of-the-art FPGA-based solutions.