Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed toward leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.

Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.

The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct anandstandard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOSnandgate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates.

In this paper, a differential to single-ended DC-coupled compact and power efficient lumped driver for single-ended optical modulators using the IHP 250 nm SiGe BiCMOS SG25H5 technology, featuring$\mathrm{f}_{\mathrm{t}}/\mathrm{f}_{\max}$of 220/290 GHz, has been analyzed and reported. The amplifier is composed of a differential to single-ended common-emitter variable gain stage, a fixed gain common-emitter stage and a cascode amplifier. Emitter followers have been used between the stages for DC leveling purposes. Peaking inductors for both input and output stages have been used to shape the frequency response in different frequency ranges, while degeneration resistors have been employed for improving the linearity of the circuit. Measurement results show that the proposed design has a low frequency gain of 15 dB and a 3 dB bandwidth of 53 GHz, along with a total harmonic distortion at 1dB compression of 8 % and an in band group delay variation of ±3 ps. Time-domain measurements show operation up to 60 Gbps non-return-to-zero and 36 GBaud 4-levels pulse amplitude modulation, together with an output voltage swing at 1 dB compression of 0.8Vppd. The fabricated circuit has a footprint of$(0.2\times 0.3)\text{mm}^{2}$and a power dissipation of 175mW resulting in a compact and power efficient DC-coupled differential to single-ended design, suitable for single-ended optical devices, which is very rare to be found in the literature.