Synthesized netlists often leave substantial room for area optimization due to the limited function diversity in standard cell libraries, which frequently results in recurring logic patterns that could be compacted through cell combination-referred to as hypercells in this work. While prior studies have demonstrated the potential of hypercell-based optimization, most lack efficient and scalable mining strategies. We present SOFA-H, a post-synthesis framework that extracts and remaps hypercells for maximum area reduction. SOFA-H (i) mines fanout-induced subgraphs and canonically encodes them using P-Representatives, (ii) selects an optimal set of hypercells with non-overlapping replacements via a one-shot weighted MaxSAT formulation, and (iii) supports high input, multi-output cells with scalable runtime. Evaluated on the EPFL benchmark suite synthesized using FreePDK45 and ASAP7, SOFA-H achieves average area reductions of 12.2% and 7.4%, respectively, and runs $380 \times$ faster on average at ASAP7 compared to the state-of-the-art method. These results demonstrate that the extracted hypercells offer a scalable and effective path to closing the area gap left by conventional synthesis.

In the field of VLSI design, accurate capacitance extraction is essential for ensuring optimal performance of integrated circuits, especially in standard cell designs. Conventional techniques, such as the 2.5D model and 3D field solver, either suffer from inaccuracies or are computationally intensive. To address these challenges, we present ResCap, an innovative approach that synergizes physics-guided linear models with advanced machine learning techniques. Rather than directly predicting the target capacitance, our method starts by employing physical principles to estimate the initial capacitance value, ensuring that predictions are grounded in well-established physical laws. Subsequently, machine learning is applied to predict residual values, thereby refining the initial estimates. This approach not only enhances accuracy and generalization but also reduces dependency on extensive training datasets. Experimental results demonstrate that ResCap significantly outperforms conventional methods on industrial standard cell designs under 4nm process technology, achieving high accuracy with an average error of 0.06% in delay and 0.16% in power. Notably, ResCap exhibits no outliers (error > 1%), whereas the conventional 2.5D extraction tool shows significant outliers of 10.95% in delay and 50.4% in power. Furthermore, our framework demonstrates remarkable efficiency, reducing extraction time by 215x compared to field solvers.

Standard cell layout design at advanced technology nodes faces a massive combinatorial explosion of transistor placement possibilities, especially when targeting optimal performance, power, and area (PPA). In this work, we propose a novel framework that integrates AllSAT-based pruning and Monte Carlo Tree Search (MCTS) to tackle this challenge efficiently. Our method first employs an AllSAT formulation that incorporates routing constraints and layout heuristics to exhaustively enumerate only the legal and promising placement solutions. This dramatically reduces the solution space while preserving high-quality candidates. We then apply a guided MCTS algorithm to explore the reduced space and identify optimal or near-optimal placements under given objectives such as total wire length (TWL). Experimental results on a diverse set of standard cells demonstrate the effectiveness of our approach. The AllSAT filtering improves average solution routability from 1.1% to 62.7%, while reducing the total placement space by over 99.9%. On top of that, our MCTS achieves a 62.2× runtime speedup over brute-force exploration, with only a 0.2% degradation in TWL quality. These results confirm that our AllSAT+MCTS framework offers a scalable and practical solution for high-quality standard cell layout synthesis.

Optimizing power, performance, and area in IC designs remains a key focus. However, the limited functionality of standard cell libraries restricts further optimization. A promising solution involves developing customized complex gates that integrate multiple basic gate functions into a single gate at the transistor level. While prior research has extensively explored transistor network optimization of the complex gates, most studies still focus on 1-stage networks, limiting the potential for deeper optimization. Furthermore, existing methodologies often neglect considering transistor placement during network synthesis, potentially leading to suboptimal area even if the transistor count is reduced. To address these limitations, we propose MuSTNet, a SAT-based exact synthesis framework that minimizing transistor networks by incorporating two key innovations: (1) multi-stage hierarchy for deeper optimization, and (2) transistor placement constraints to simultaneously minimize both transistor count and physical area. Experimental results demonstrate that MuSTNet surpasses previous studies, achieving an 18% reduction in transistor count for 4-input P-class functions and a 12.9% reduction for multi-output functions. When applied to an industrial library benchmark, MuSTNet yields a 6.3% area reduction compared to the approach neglecting placement constraints. Moreover, MuSTNet has been applied to complex gate generation, allowing simultaneous functional and topological optimization at the transistor level. Compared to traditional cell-level design, this approach reduces transistor count by 12.3% and area by 21.4%, demonstrating its potential in advanced IC design.

To optimize power, performance, and area (PPA) of IC designs, standard cell has evolved from basic to complicated designs, resulting in complex multi-height structures. Although extensive research on single-height cell automatic synthesis, multi-height cell studies are still limited due to the extremely large solution space. In this paper, we present MAXCell, a PPA-directed standard cell layout optimization framework for both single-height and multi-height designs using anytime MaxSAT with constraint learning. This framework incorporates two novel techniques: (1) learning additional constraints from the original constraints database to accelerate convergence during problem-solving and (2) integrating a genetic algorithm with a ranking model to dynamically guide the router towards the PPA goal directly during optimization. Experimental results indicate that MAXCell outperforms previous studies that target wire length optimization, achieving a 5.5% power reduction in evaluations of 33 multi-bit flip-flop designs beyond 4nm technology. Furthermore, compared to an industrial library designed by experienced engineers, MAXCell provides a 3.5% power optimization benefit and drastically reduces the delivery time from multiple days to a mere few hours (21.6X faster). This emphasizes its efficiency and its potential in modern integrated circuit design.

Aging is an important determinant for the reliability of circuit designs and has been addressed by a number of protection techniques based on static timing analysis (STA). The timing reported by STA, however, is often too optimistic without considering the functional behavior of the circuit. Furthermore, signal probability has also been found to be a significant factor in the aging effect. As such, we present in this paper a timing-critical path analysis that takes function and aging into account as well as signal probability. Functional timing analysis (FTA) eliminates the false paths and generates more accurate timing. Furthermore, machine learning can be used to build models for predicting the timing of each cell for various aging lifetimes and signal probabilities. Experimental results indicate that there can be a difference of up to 6% on path delay between STA and FTA. The path ranks also differ for most of the benchmark circuits after considering aging with signal probability, resulting in the delay differences of up to 6.12 %. In conclusion, it is necessary to consider function, aging, and signal probability simultaneously when analyzing timing-critical paths in a circuit design.