Over the years, several clock and data recovery architectures have been proposed for wireless Amplitude Shift Keying (ASK) transmitted signals. State-of-the-art architectures mainly rely on synchronous phase-locked loop circuits or self- sampling systems, both resulting in large area consumption. This work presents a novel CMOS architecture for Clock and Data Recovery (CDR) in miniaturised and wirelessly powered implants. The proposed CDR architecture works at 433.92 MHz and includes: an ASK-demodulator, an on-chip oscillator, a power-on-reset, a control and a recovering block operating in feedback-loop. The ASK-demodulator works for a data rate as high as 6 Mbps and a modulation index in the range of 9-30%. A novel communication protocol is presented for a separated clock and data transmission. The entire CDR architecture occupies$17 \times 89 \mu m^{2}$and consumes$15.01 \mu W$while operating with a clock rate of 6 Mbps.

We present here the first ever-reported direct computation of the cancer risk on cancer markers simultaneously detected by memristors. The novel approach in cancer diagnostics here proposed is based on the fusion of the three actions of sensing, computing and memory in a single-kind of device. So, this paper proposes the new concept of in-memory sensing as a disruptive approach in edge-computing. The concept is demonstrated by showing a well-known case in cancer diagnostics: the estimation of the risk of prostate cancer based on the simultaneous measure of Prostate Specific Antigen (PSA) and its Membrane isoform (PSMA).

With rapid development of Internet of Things, there is high demand for miniaturized biochemical sensors, which enable a digital-controlled connection and portable integration. In this work, we report an ASIC interface for capacitive micromachined ultrasonic transducers (CMUTs), offering multi-channel monitoring of frequency shifts and supplying high-voltage (HV) source. Previously reported CMUTs-based biochemical sensors required a peripheral power source to provide a DC driving voltage (e.g.,10-50 V), which was higher than the common circuit supply (e.g., 1.2-5 V). This resulted in additional circuit footprints and parasitic effects, especially for high frequency. Instead, we proposed an ASIC interface designed through TSMC $0.18-\mu{m}$ HV BCD process with a die size of 2×2 mm2. Four-channel oscillators are proposed to track frequency shifts of CMUT resonators with a resonant frequency of 1.8MHz, and a start-up period up to $100\mu$ s and a phase noise of −38.73dBc/Hz at low offset of 100 Hz were observed, while consuming an average total power of $142.12\mu\mathrm{W}$ in continuous mode. A PMOS-based HV charge pump is presented to generate a voltage boosting of ~50 V with a 1.8-V input source, which enables tuning clock signals by implementing four-parallel ring oscillators with the frequency of 20-50 MHz. The proposed ASIC integrated with CMUTs is a molecules.