In this brief, we present a fractional-N multiplying delay locked loop (MDLL) which uses a reference triggered ring oscillator (RTRO) as a coarse digital-to-time converter (DTC) to reduce a required fine DTC range by 1/10, improving its linearity. The RTRO’s period is a programmed offset from the MDLL period so that each RTRO cycle effectively adds a delay to the reference clock. As a result, the fine DTC range only needs to cover the programmable coarse step, allowing > 9x range reduction, relaxing the design requirements of the DTC. The RTRO and MDLL periods are regulated by frequency locked loops (FLLs) that use a bang-bang phase detector (BBPD) to detect errors. Delay Locked Loops (DLLs) are used to regulate the DTC delays and absorb the offsets introduced by each BBPD. An LMS algorithm-based background calibration is used for correcting the fine DTC gain. To prove the concept, we designed the MDLL in a 65nm CMOS process. Verilog simulation with block-level models based on parasitic-layout transistor-level simulation results are used to evaluate the performance. A RMS jitter of 141.3fs was achieved at 3.00005GHz with a 50MHz reference clock, achieving a -246.7 dB FoM. The worst case fractional spur and reference spur are -69.2 dBc and -55.5 dBc, respectively.

This work presents an output-capacitor-free synthesizable LDO with a novel hybrid controller architecture to overcome poor PSRR problem of Digital LDOs (DLDOs) at low frequencies. The architecture employs a synthesizable PID controller as the digital controller and uses a low-bandwidth amplifier to modulate the drive strength of the digital current switches in steady state. The hybrid LDO is fabricated in a 65nm process and occupies an area of 0.09164mm2. The LDO has an output current range of 1mA - 82mA at 50mV dropout, a PSRR or -12.25dB @1kHz and achieves a 3.32ps fast response time with 99.87% peak current efficiency resulting in a FOM of 4.3fs.

This work presents a methodology to automate the design and layout implementation of a low dropout (LDO) regulator from the user specified performance requirements. The proposed methodology adopts LDO architectures compatible with cell-based design process, as the template architectures to achieve the synthesis of LDO analog specifications. An auxiliary-cell (auxcell) library with mixed signal components compatible with standard-cell grid placement, is implemented to enable the cell-based design automation. The automation process includes a technology-agnostic modeling step to determine the performance of auxcells and the overall LDO design, making this methodology highly robust. A python based LDO generator tool using the proposed methodology is implemented to demonstrate LDO designs in 130nm, 65nm and 12nm CMOS processes. Similar to that of digital standard cell libraries, there is a one-time cost of auxcell library preparation when porting the LDO generator to a new technology node. A commercial place-and-route tool is then used to implement the layout of both the digital and mixed-signal blocks, outputting final GDS with no additional custom layout required. The generator has a baseline design with I-controller, for synthesis of DC input specifications (input voltage, dropout, ripple, output load and output cap). Synthesis of transient input (max undershoot/overshoot, min load step time) specifications is achieved by integrating synthesizable P/PD control loops with the baseline. LDO designs with fast transient response, minimum load transition times of 2ns and FOMs >59.2fs, have been implemented and verified with post-PEX simulations using this generator.

This work presents an open-source methodology to automate the design and layout of a low dropout (LDO) regulator from high-level performance specifications. LDO designs with this methodology have been demonstrated in commercial 65nm, 12nm, 130nm processes and the open-source 130nm Skywater PDK. The tool currently supports LDO designs with 50mV/100mV dropout for an input voltage range of 0.6V-1.3V (130nm and 65nm), 0.6V-0.9V (12nm), 1.8V-3.3V (Skywater 130nm) and a maximum load current ranging from 0.5mA-25mA (130nm and 65nm), 1mA-20mA (12nm), 0.5mA-50mA (Skywater 130nm). Cell-based design approach is adopted using an auxiliary cell library to enable mixed-signal design synthesis. A port to a new technology only requires a one-time manual layout for auxiliary library generation. The design automation includes a technology-agnostic modeling step and generates the LDO layout automatically. A bi-directional shift register based DLDO with a 1-bit comparator and a stochastic flash ADC (achieving 15x faster settling time) for error detection has been generated using the tool and validated using silicon measurements from 65nm process. LDO designs with different switch types and load configurations have been fabricated in open-source Skywater 130nm.

We present the world's first autonomous mixed-signal SoC framework, driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process-agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog blocks using a cell-based design methodology. Our approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different processes and requires no-human-in-the-Ioop, dramatically accelerating design time.