Energy harvesting is considered to be a substitute for batteries in many modern systems. Systems based on energy harvesting receive environmental energies from sources such as sun, radio frequency, wind, vibration, etc, and convert them to electrical energy to be used by the capacitor of the system or feed the CPS system directly. Despite its advantages, energy harvesting comes with some limitations, such as the instability of the received energy, which means that the energy may not be received for a moment due to environmental conditions during energy harvesting. Therefore, due to not receiving enough energy, the system function may face problems, which can lead to system shutdown and data loss. To prevent program execution interruption caused by frequent power interruptions in systems based on energy harvesting, these systems use NVP. Saving the state in the NVP is done through non-volatile registers and memories that can hold the contents until the power is restored. However, systems based on energy harvesting and NVPs also have challenges such as frequent backups’ energy consumption, slow program forward progress, and loss of data. In this paper, we propose TVTAC, a framework for energy harvesting-based NVP CPS systems. TVTAC modifies conventional NVP’s cache architecture to efficiently work with newly introduced operational mode to prevent unnecessary backup operations. Furthermore, TVTAC is equipped with an NVP’s specific approximation unit that controls the approximation knobs during the approximate data cache accesses in order to save more energy. The simulation results show that TVTAC improves forward progress by 28% in the best case and 12% on average, compared to similar methods. From an energy consumption perspective, TVTAC reduces energy consumption by 43.5% in the best case and 28.5% on average.

The stochastic switching feature of Spin-Transfer Torque Magnetic RAM (STT-MRAM) provides an attractive knob to trade quality for energy consumption in approximate computing applications. Indeed, the quality of STT-MRAM functionalities (mainly write operation) is increased by consuming more energy to achieve a more stable write. On the other hand, in approximate computing applications, we do not need 100 percent quality for all of the data. Accordingly, in recent years, several approaches have been proposed to find a balance between output threshold quality and energy consumption in approximate computing applications employing STT-MRAM on-chip memories. While approximate computing application output qualities are highly affected by the fluctuations of the environmental-conditions or input variations, none of the previously proposed approaches have considered the effects of these fluctuations on the output quality. In this article, we propose NOSTalgy, a closed-loop cross-layer approach to dynamically trade off the quality of STT-MRAM based cache memories for energy saving in approximate computing applications. NOSTalgy utilizes a feedback managed fine-grained cache-line-level actuation knobs with different levels of quality for individual write accesses. These knobs are adjusted with the support of the operating system and programmer at run-time. Our experimental results using a set of benchmarks show that NOSTalgy satisfies the output quality thresholds while delivering up to 52 percent energy savings with negligible performance and area overheads.

STT-MRAM is regarded as an extremely promising NVM technology for replacing SRAM-based on-chip memories. While STT-MRAM memories benefit from ultra-low leakage power and high density, they suffer from some reliability challenges, namely, read disturbance, write failure, and retention failure. The write failure; storing a wrong value in an STT-MRAM cell during a write operation, is the most crucial reliability challenge. In this article, we propose ROCKY; a robust architecture equipped with efficient replacement policies for STT-MRAM-based cache memory hierarchy to improve the robustness of STT-MRAM part against the write failures. ROCKY reduces susceptible transitions in STT-MRAM cache memories leading to more reliable STT-MRAM write operations. The simulation results through comparison with traditional cache memory hierarchy demonstrate ROCKY decreases the WER of STT-MRAM cache memories by up to 35.4 percent while imposing less than 1 percent performance overhead to the system.