Most modern multi-core edge devices work in outdoor situations with limited power supplies like energy harvester and batteries. Therefore, energy consumption is a fundamental issue in which the memory subsystem has a significant role. Scratchpad memories (SPM) can provide a broad potential for energy saving. Still, due to the insufficient SPM capacity in such edge devices, a rigorous SPM data allocation scheme is necessary to reduce the energy consumption of the memory subsystem. Emerging non-volatile memories (NVMs) are very useful to reduce the energy consumption of the memory subsystem. Compared with SRAM, NVMs have lower leakage power and higher density, but the read and write latencies of the NVMs are higher than the SRAM. Therefore, embedded and edge devices can take advantage of hybrid SPM composed of both NVM and SRAM to achieve further energy saving. This paper proposes MASTER, a task mapping, task scheduling, and dynamic SPM allocation scheme that efficiently utilizes the hybrid SPM space. To this end, we model the hybrid SPM allocation on a multi-core system with integer linear programming formulation to minimize the energy consumption of the memory subsystem. Experimental results show that MASTER improves the energy saving of the memory subsystem by up to 34 percent compared to EADA, which is a heuristic dynamic data allocation algorithm for multi-core systems with hybrid SPM.

In Mixed-Criticality (MC) systems, there are often multiple Worst-Case Execution Times (WCETs) for the same task, corresponding to system operation mode. Determining the appropriate WCETs for lower criticality modes is non-trivial; while on the one hand, a low WCET for a mode can improve the processor utilization in that mode, on the other hand, using a larger WCET ensures that the mode switches are minimized, thereby maximizing the quality-of-service for all tasks, albeit at the cost of processor utilization. Although there are many studies to determine WCET in the highest criticality mode, no analytical solutions are proposed to determine WCETs in other lower criticality modes. In this regard, we propose a scheme to determine WCETs by Chebyshev theorem to make a trade-off between the number of scheduled tasks at design-time and the number of dropped low-criticality tasks at runtime as a result of frequent mode switches. Our experimental results show that our scheme improves the utilization of state-of-the-art MC systems by up to 85.29%, while maintaining 9.11% mode switching probability in the worst-case scenario.

Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories instead of conventional SRAM due to their lower leakage power consumption and smaller cell area. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems to resume their execution without a large startup delay. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system if not managed correctly. In this article, we present a predictable fully non-volatile data memory for real-time embedded systems which improves both worst-case execution time (WCET) and performance of the system using a hybrid hardware-software solution. As part of this solution, we add a special write buffer to the memory controller and adopt a multi-bank memory configuration which improves the overall latency of write operations. Since write buffers usually help with the performance problem but they make WCET estimation more complex, we also present a new low-overhead software-based optimization technique that makes the proposed system more predictable without imposing considerable overhead. Furthermore, we present the WCET analysis algorithm which can be used to estimate the WCET of applications during the design time. The results show that compared to a hybrid SRAM-NVM architecture, the proposed solution improves the WCET and performance by 33 and 47 percent, respectively.

The energy efficiency of emerging nonvolatile processors equipped with FRAM-SRAM memory makes them a promising solution for energy harvesting systems. To enable correct functionality and forward progress with an unreliable power supply, the system must accumulate sufficient energy in the capacitor to execute tasks atomically, even in the worst case scenario. Due to the large gap between the average and worst case energy consumption of tasks, state-of-the-art approaches like eM-map require a large capacitor to execute tasks on the SRAM. However, the size, cost, and charging time of the capacitor are major concerns in the energy harvesting systems. In this article, we proposed CHANCE, a capacitor charging management scheme that improves the capacitor size and average response time of an energy harvesting system. CHANCE analyses the energy consumption of tasks to set an appropriate capacitor size to make a balance between capacitor charging time and failure rate for each task. The results show that CHANCE improves the response time of state-of-the-art approaches up to 68% with a five times smaller capacitor.