Graph neural networks have recently emerged as a promising approach for low-power and low-latency event-vision applications. Such event-graphs naturally exploit the sparsity of event-data and incorporate the temporal detail captured by event-based sensors directly into the edge features used in graph convolution. In this paper we study the promise of event-graphs for processing data from other event-based modalities beyond vision. Specifically, we describe how the approach can be adapted to the spectro-temporal domain to perform event-audio classification. We evaluate the approach using the spiking Heidelberg digits dataset and achieve a test accuracy of 94.3%. This is notably better than many state of the art spiking neural networks despite, in many cases, requiring an order of magnitude fewer parameters. Event-graph neural networks promise to be a powerful, general approach for processing a variety of event-based modalities, not only vision.

Spiking Neural Networks (SNNs) can unleash the full power of analog Resistive Random Access Memories (RRAMs) based circuits for low power signal processing. Their inherent computational sparsity naturally results in energy efficiency benefits. The main challenge implementing robust SNNs is the intrinsic variability (heterogeneity) of both analog CMOS circuits and RRAM technology. In this work, we assessed the performance and variability of RRAM-based neuromorphic circuits that were designed and fabricated using a 130 nm technology node. Based on these results, we propose a Neuromorphic Hardware Calibrated (NHC) SNN, where the learning circuits are calibrated on the measured data. We show that by taking into account the measured heterogeneity characteristics in the off-chip learning phase, the NHC SNN self-corrects its hardware non-idealities and learns to solve benchmark tasks with high accuracy. This work demonstrates how to cope with the heterogeneity of neurons and synapses for increasing classification accuracy in temporal tasks.

Dedicated hardware implementations of spiking neural networks that combine the advantages of mixed-signal neuromorphic circuits with those of emerging memory technologies have the potential of enabling ultra-low power pervasive sensory processing. To endow these systems with additional flexibility and the ability to learn to solve specific tasks, it is important to develop appropriate on-chip learning mechanisms. Recently, a new class of three-factor spike-based learning rules have been proposed that can solve the temporal credit assignment problem and approximate the error back-propagation algorithm on complex tasks. However, the efficient implementation of these rules on hybrid CMOS/memristive architectures is still an open challenge. Here we present a new neuromorphic building block, called PCM-trace, which exploits the drift behavior of phase- change materials to implement long lasting eligibility traces, a critical ingredient of three-factor learning rules. We demonstrate how the proposed approach improves the area efficiency by > 10× compared to existing solutions and demonstrates a technologically plausible learning algorithm supported by experimental data from device measurements.