Custom hardware instructions are frequently used to accelerate software. However, the number of active custom instructions - and speedup opportunities - are limited in resourceconstrained systems, such as those using small embedded FPGAs (eFPGAs). Hence, it is desirable to be able to dynamically reconfigure this resource to allow an application to change the accelerator logic. While an existing method called CX Table is described the Draft CX Specification to manage accelerators, it is not suitable for lightweight embedded systems because (1) virtual memory is required to isolate processes, and (2) an implied table lookup is required when switching custom instruction sets. This paper presents CIA Direct, a lightweight alternative to CX Table. It moves the table into a privileged control register to avoid virtual memory and external memory accesses. It provides inter-process virtualization of accelerator state, but intra-process virtualization has performance limitations. This paper also describes CxBex, the first ASIC implementation of CIA Direct. It contains a hard RISC-V processor with an eFPGA to support multiple custom instruction accelerators under dynamic reconfiguration. Unique to CxBex, context switching keeps multiple independent state context intact in eFPGA block during reconfiguration. Intended for lightweight embedded systems, this work demonstrates that the CIA Direct approach is simpler, reduces CPU complexity, eliminates dependence on external memory, and manages dynamic reconfiguration using exceptions.

At the end of CMOS-scaling, the role of architecture design is increasingly gaining importance. Supporting this trend, customizable embedded FPGAs are an ingredient in ASIC architectures to provide the advantages of reconfigurable hardware exactly where and how it is most beneficial. To enable this, we are introducing the FABulous embedded open-source FPGA framework. FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated FPGA fabrics. The framework provides templates for logic, arithmetic, memory, and I/O blocks that can be easily stitched together, whilst enabling users to add their own fully customized blocks and primitives. The FABulous ecosystem generates the embedded FPGA fabric for chip fabrication, integrates Yosys, ABC, VPR and nextpnr as FPGA CAD tools, deals with the bitstream generation and after fabrication tests. Additionally, we provide an emulation path for system development. FABulous was demonstrated for an ASIC integrating a RISC-V core with an embedded FPGA fabric for custom instruction set extensions using a TSMC 180nm process and an open-source 45nm process node.