Compute-in-memory (CIM) technology has emerged as a promising solution to address the computational demands of deep neural network (DNN) models, which require substantial multiply-accumulate (MAC) operations. However, there is a growing need for reconfigurable CIM architectures that can support both integer (INT) and floating-point (FP) operations within a single design. This flexibility is crucial for optimizing efficiency and resource utilization, especially in DNN applications involving mixed-precision computations. In this work, we propose a reconfigurable precision digital macro design that accelerates MAC computations while supporting INT4, INT8, and FP8 configurations within the same architecture. Both signed and unsigned operations are supported in INT mode. To enhance performance, the proposed design uses a parallel-input approach and a mantissa parallel-alignment technique in FP mode. The macro is implemented in 40nm CMOS technology. It achieves a peak throughput of 7123.48 GOPS in INT4 mode and 1187.25 GFLOPS in FP8 mode, with peak energy efficiencies of 367.45 TOPS/W and 23.14 TFLOPS/W, respectively.

In-memory computing (IMC) is a promising approach for accelerating multiply and accumulate (MAC) operations, which are the primary calculations used in artificial intelligence (AI). The demand for flexible architectures supporting different bit precisions in MAC computations becomes evident. This flexibility balances adapting to specific model requirements and optimizing design performance efficiency. As such, in this paper, we propose a reconfigurable IMC macro design, utilizing 8T static random-access memory (SRAM) bit-cells in 65nm technology, to efficiently perform MAC operations while supporting three bit precisions: 2, 3, and 4 bits for each of the input, weight, and output. The proposed 64×180 macro achieves a normalized peak throughput of 13.82 TOPS, a normalized peak energy efficiency of 291.66 TOPS/W, and a normalized peak area efficiency of 165.98 TOPS/mm2.

DNA pattern matching is a key technique applied in many bioinformatics applications. Recently, this technique has become very popular and is widely used for genetic disease diagnosis, where finding the number of consecutive repeats of a specific DNA pattern indicates the type and intensity of the patient's disorder. However, the remarkable growth of DNA data exacerbates the latency and power consumption required to perform DNA pattern matching. In this work, we propose a hardware accelerator design to detect the presence of different diseases efficiently using DNA pattern matching. We propose a novel CAM cell using binary memristors for reliable and robust data encoding. The proposed architecture consists of two main building blocks the Content-addressable memory (CAM) and pattern detector circuits in addition to the needed peripheral circuits for CAM read, write and match operation. CMOS PTM 45nm technology was used to design and simulate the full architecture. The evaluation of the proposed design shows$\sim 2\times$improvement in energy-delay-area product compared to the state-of-art work in the literature, in addition to robustness against noise and process variations.