Ising machines model nature dynamics to solve nondeterministic polynomial time (NP) hard combinatorial optimization problems (COPs). Because physical systems can naturally minimize their energy, these Ising machines have higher efficiency as compared to von Neumann architectures. This makes Ising machines attractive for tackling complex optimization problems mapped to the Ising Hamiltonian. In this paper, a highly scalable CMOS-compatible Ising machine design is proposed that leverages ring oscillator coupling under second-order sub-harmonic injection locking (SHIL). The proposed design is smaller and faster as compared to the state-of-the-art based on initial findings. Unlike traditional designs that use external injection locking signals or bulky LC oscillators, the proposed approach integrates both spin representation and SHIL signal generation directly on-chip using lightweight ring oscillators. The phase readout process is simplified by utilizing XOR gates for efficient spin readout. The initial results, obtained through SPICE simulations on 28nm FDSOI technology, confirm the feasibility of the proposed design. This approach presents a compact high-speed Ising machine with potential applications in solving a wide range of NP-hard problems.

Pseudo-random number generators (PRNGs) are essential in a wide range of applications, from cryptography to statistical simulations and optimization algorithms. While uniform randomness is crucial for security-critical areas like cryptography, many domains, such as simulated annealing and CMOS-based Ising Machines, benefit from controlled or nonuniform randomness to enhance solution exploration and optimize performance. This paper presents a hardware PRNG that can simultaneously generate multiple uncorrelated sequences with programmable statistics tailored to specific application needs. Designed in 65nm process, the PRNG occupies an area of approximately 0.0013mm2and has an energy consumption of 0.57pJ/bit. Simulations confirm the PRNG's effectiveness in modulating the statistical distribution while demonstrating high-quality randomness properties.

Ising machines have shown great promise in solving combinatorial optimization problems (COPs) using nature-inspired computation with higher speed and efficiency over traditional von Neumann computing systems. CMOS-based implementations combine the maturity and scaling ability of CMOS with the efficacy of Ising machines. In this paper, a low-density parity-check (LDPC) decoding solution is implemented with a CMOS-based resistively-coupled Ising machine known as (QuBRIM), using multi-body interactions among CMOS-based Ising machine nodes for the first time. State-of-the-art CMOS-based Ising implementations currently utilize order reduction to solve problems with higher-than-quadratic terms. In this paper, a new mechanism is proposed to implement higher-than-quadratic terms on Ising machines without the need for order reduction. The proposed methodology is implemented and verified with CMOS technology using 45 nm Generic PDK (GPDK). High accuracy rates are reported for the LDPC decoder based on the proposed methodology, comparable to Normalized Min-Sum, Offset Min-Sum, and Layered Belief-Propagation decoders, with a bit error rate (BER) as low as$4 \times 10^{-8}$at a signal-to-noise ratio (SNR) of 4dB. Furthermore, the proposed LDPC decoder attains a normalized energy efficiency (NEE) of 1.29 pJ/bit/iteration, surpassing the state-of-the-art decoders by a minimum factor of 2.4 and as much as 7.6 times.

The Ising-physical unclonable function (PUF) is a recent PUF structure formed of a network of APUFs inspired by the Ising model. A large challenge–response pair (CRP) space with high resilience against machine learning modeling attacks can be attained due to the unique arrangement. These advantages, however, are achieved at the cost of a large area overhead. In this article, a reconfigurable Ising-PUF is introduced with several new design knobs to generate a much larger CRP space within a smaller area. A 25% increase in the number of challenge bits can be achieved for a design that occupies 30% of the conventional Ising-PUF area. With the proposed lightweight area-efficient design, up to 5.6 times lower area per CRP can be achieved compared to the existing design. Several improvements are proposed that leverage the large design space, enabling dynamic tradeoffs between the area and CRP pool with the proposed flexible customization of Ising-PUFs. A detailed analysis of this improved design space is explored for different parameters. The state-of-the-art machine learning modeling attacks are investigated, and the Ising-PUF structure is shown to be resilient.