Three-dimensional integrated circuits (3D-ICs) is a cutting-edge design methodology of placing the circuitry vertically aiming for a high-speed and energy-efficient system with the smallest design area. In this article, a novel 3-D neuromorphic system is proposed and analyzed, which utilizes the fabricated two-layer memristor as the electronic synapses in a spiking neural network (SNN). The two-layer structure of the memristors leads to a significant improvement in the design area ($2\times $), power consumption ($1.48 \times $), and latency ($2.58 \times $), compared to the traditional one-layer configuration. Meanwhile, the heat dissipation layers are added to our memristors reducing 30% cycle-to-cycle switching variation. Our memristive synapses are utilized for storing the exported weights of the SNNs that have threshold function as the activation function. The proposed neuromorphic system is evaluated using a hardware–software co-design approach importing the weights of SNNs into NeuroSIM. The simulation results demonstrate the significant improvement of memristive synapses on design area, power consumption, and latency, compared with the static random-access memory (SRAM) and other state-of-the-art memristive synapses (10%–66%).

Deep neural networks (DNNs), a brain-inspired learning methodology, requires tremendous data for training before performing inference tasks. The recent studies demonstrate a strong positive correlation between the inference accuracy and the size of the DNNs and datasets, which leads to an inevitable demand for large DNNs. However, conventional memory techniques are not adequate to deal with the drastic growth of dataset and neural network size. Recently, a resistive memristor has been widely considered as the next generation memory device owing to its high density and low power consumption. Nevertheless, its high switching resistance variations (cycle-to-cycle) restrict its feasibility in deep learning. In this work, a novel memristor configuration with the enhanced heat dissipation feature is fabricated and evaluated to address this challenge. Our experimental results demonstrate our memristor reduces the resistance variation by ~ 30% and the inference accuracy increases correspondingly in a similar range. The accuracy increment is evaluated by our deep delay-feed-back reservoir computing (Deep-DFR) model. The design area, power consumption, and latency are reduced by ~48%, ~42%, and ~67%, respectively, compared to the conventional static random-access memory technique (6T). The performance of our memristor is improved at various degrees (~13%-73%) compared to the state-of-the-art memristors.