Argo is a packet-switched, source routed network-on-chip (NoC) using time-division multiplexing to provide worst-case execution time bounds, used in the T-CREST project. Patmos, the processor in the T-CREST project, is implemented in the modern hardware construction language Chisel, but Argo is implemented in VHDL. This makes multicore simulation difficult, and complicates incorporation of Argo with Patmos. This paper presents a translation of Argo from VHDL to Chisel, moving the entire T-CREST platform to one hardware description language. In addition to porting Argo, constrained random unit tests have been added for every component of the NoC, making it easier to verify that further development does not break existing functionality. The NoC was synthesized for a 2×2 platform and implemented on the Altera DE2-115 development board. The Chisel version of Argo consumes marginally fewer hardware resources and is able to operate at the same frequency as the VHDL version. By translating Argo to Chisel, further development of the T-CREST platform will be simplified, as only one language is used for all hardware components in the project. By adding unit tests to Argo, further development of the NoC will be more efficient and less likely to introduce errors.

This paper explores using the hardware construction language Chisel to describe, implement, and test asynchronous circuits. The Chisel language supports clocked registers and the use of multiple clocks. It is hence capable of describing asynchronous designs that are built from clocked flip-flops and logic, such as circuits using the asynchronous (phase-decoupled) click-element template that we target in this paper. Previous work has used VHDL to describe a library of asynchronous data-flow components as well as an example circuit demonstrating the use of the components. In this paper, we re-implement this work using Chisel and compare against VHDL. As we see, Chisel offers more efficient and elegant support for describing asynchronous handshake channels and for connecting components. Compared to the VHDL version, the code is reduced by up to 80 %. The example circuit computes the greatest common divisor of two integers, and it is synthesized and tested on an FPGA board. All code is open source giving those interested easy access to asynchronous design and prototyping.

Topology Optimization is a class of structural optimization problems, where the classical goal is to find the best layout of a structure ensuring that it can withstand a set of prescribed forces, while being as light as possible. Since this class of optimization problems are computationally expensive, a vast amount of research is directed at how to increase the speed at which these problems can be solved. Previous work on accelerating topology optimization problems includes designing more efficient algorithmic approaches and better utilizing hardware resources. However, to the best of our knowledge, no previous attempts have been made to accelerate topology optimization using a hardware accelerator implemented on an FPGA. This paper presents a hardware accelerator for topology optimization, designed to solve compliance minimization problems in three dimensions. The accelerator is implemented as an application-specific instruction set processor, using a custom instruction set architecture designed specifically for the minimum compliance problem. The developed accelerator is able to solve problems 4.8–8.2 times faster than a modern computer, while operating at a fraction of the clock frequency. Although the current accelerator has only been proven to work on coarse meshes, it is reasonable to assume that the speedup will also carry over to larger optimization problems. This indicates that FPGA-based acceleration of topology optimization problems is viable.

Ever-increasing performance demands are pushing hardware designers towards designing domain-specific accelerators. This has created a demand for improving the overall efficiency of the hardware design and verification cycles. The design efficiency was improved with the introduction of Chisel. However, verification efficiency has yet to be tackled. One method that can increase verification efficiency is the use of various types of coverage measures. In this paper, we present our open-source, coverage-related verification tools targeting digital designs described in Chisel. Specifically, we have created a new method allowing for statement coverage at an intermediate representation of Chisel, and several methods for gathering functional coverage directly on a Chisel description.