Functional verification accounts for a significant portion of the design effort in modern digital hardware development. As projects grow in complexity, maintaining and extending verification code becomes increasingly difficult, particularly in collaborative environments. This calls for a methodology that defines a clear structure and promotes reuse through modular, composable testbench components. In this paper, we present a Scala-based verification framework that adopts a structured approach to building modular and reusable testbenches, inspired by the Universal Verification Methodology (UVM). We analyze the core mechanisms through which UVM achieves modularity and reusability, and identify a minimal subset that provides equivalent functionality with reduced complexity. The result is a lightweight verification framework in Scala 3 using Verilator as a backend, which allows for simple unit-test-style testing as well as complex UVM-style testbench environments.

This paper explores using the hardware construction language Chisel to describe, implement, and test asynchronous circuits. The Chisel language supports clocked registers and the use of multiple clocks. It is hence capable of describing asynchronous designs that are built from clocked flip-flops and logic, such as circuits using the asynchronous (phase-decoupled) click-element template that we target in this paper. Previous work has used VHDL to describe a library of asynchronous data-flow components as well as an example circuit demonstrating the use of the components. In this paper, we re-implement this work using Chisel and compare against VHDL. As we see, Chisel offers more efficient and elegant support for describing asynchronous handshake channels and for connecting components. Compared to the VHDL version, the code is reduced by up to 80 %. The example circuit computes the greatest common divisor of two integers, and it is synthesized and tested on an FPGA board. All code is open source giving those interested easy access to asynchronous design and prototyping.

Ever-increasing performance demands are pushing hardware designers towards designing domain-specific accelerators. This has created a demand for improving the overall efficiency of the hardware design and verification cycles. The design efficiency was improved with the introduction of Chisel. However, verification efficiency has yet to be tackled. One method that can increase verification efficiency is the use of various types of coverage measures. In this paper, we present our open-source, coverage-related verification tools targeting digital designs described in Chisel. Specifically, we have created a new method allowing for statement coverage at an intermediate representation of Chisel, and several methods for gathering functional coverage directly on a Chisel description.