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Ryan Piersma

dblp:286/7968 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2022
0009-0005-6132-1216ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 66% Processor architecture and microarchitecture · 25% Memory systems · 9%
Network and information security
2 papers
Systems and software security · 84% Hardware security and side channels · 16%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Systems and software security › memory safety › hardware-enforced memory safety
memory tagging
0.612022
Revisiting Residue Codes for Modern Memories · MICRO 2022
Hardware reliability and fault tolerance › error correction
error-correcting codes
0.612022
Revisiting Residue Codes for Modern Memories · MICRO 2022
Hardware reliability and fault tolerance › arithmetic codes
residue codes
0.612022
Revisiting Residue Codes for Modern Memories · MICRO 2022
Systems and software security › memory safety
hardware-enforced memory safety
0.512021
No-FAT: Architectural Support for Low Overhead Memory Safety Checks · ISCA 2021
Systems and software security
memory safety
0.512021
No-FAT: Architectural Support for Low Overhead Memory Safety Checks · ISCA 2021
Processor architecture and microarchitecture
hardware-assisted security
0.512021
No-FAT: Architectural Support for Low Overhead Memory Safety Checks · ISCA 2021
Memory systems › DRAM
rowhammer
0.212022
Revisiting Residue Codes for Modern Memories · MICRO 2022
Hardware reliability and fault tolerance
soft errors
0.212022
Revisiting Residue Codes for Modern Memories · MICRO 2022
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre
0.112021
No-FAT: Architectural Support for Low Overhead Memory Safety Checks · ISCA 2021
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack
0.112021
No-FAT: Architectural Support for Low Overhead Memory Safety Checks · ISCA 2021

Methods — techniques the papers use, named apart from their topics

fuzz testing · 1.0binning memory allocator · 1.0
YearPublicationVenuePosition
2022 Revisiting Residue Codes for Modern Memories
abstract
Residue codes have been traditionally used for compute error correction rather than storage error correction. In this paper, we use these codes for storage error correction with surprising results. We find that adapting residue codes to modern memory systems offers a level of error correction comparable to traditional schemes such as Reed-Solomon with fewer bits of storage. For instance, our adaptation of residue code – MUSE ECC – can offer ChipKill protection using approximately 30% fewer bits. We show that the storage gains can be used to hold metadata needed for emerging security functionality such as memory tagging or to provide better detection capabilities against Rowhammer attacks. Our evaluation shows that memory tagging in a MUSE-enabled system shows a 12% reduction in memory bandwidth utilization while providing the same level of error correction as a traditional ECC baseline without a noticeable loss of performance. Thus, our work demonstrates a new, flexible primitive for co-designing reliability with security and performance.
Evgeny Manzhosov, Adam Hastings, Meghna Pancholi, Ryan Piersma, M. Tarek Ibn Ziad, Simha Sethumadhavan
MICRO4
2021 No-FAT: Architectural Support for Low Overhead Memory Safety Checks
abstract
Memory safety continues to be a significant software reliability and security problem, and low overhead and low complexity hardware solutions have eluded computer designers. In this paper, we explore a pathway to deployable memory safety defenses. Our technique builds on a recent trend in software: the usage of binning memory allocators. We observe that if memory allocation sizes (e.g., malloc sizes) are made an architectural feature, then it is possible to overcome many of the thorny issues with traditional approaches to memory safety such as compatibility with unsecured software and significant performance degradation. We show that our architecture, No-FAT, incurs an overhead of 8% on SPEC CPU2017 benchmarks, and our VLSI measurements show low power and area overheads. Finally, as No-FAT’s hardware is aware of the memory allocation sizes, it effectively mitigates certain speculative attacks (e.g., Spectre-V1) with no additional cost. When our solution is used for pre-deployment fuzz testing it can improve fuzz testing bandwidth by an order of magnitude compared to state-of-the-art approaches.
M. Tarek Ibn Ziad, Miguel A. Arroyo, Evgeny Manzhosov, Ryan Piersma, Simha Sethumadhavan
ISCA4