The development and comparison of two trace-driven simulation models for microsystems with tightly coupled, shared-bus multiprocessors is presented. One model monitors the complete activities of processors, private caches, global bus, and main memory, while the other first abstracts local bus activities of processors, and then takes care of the multiprocessing interaction. The second model provides a means to move more quickly within the design space, while the first model can be used to select a final optimized design. Examples are presented to illustrate how these simulation models can help a complex choice among architectures, system configurations, and chip parameters for the design of an optimized microsystem.>

A key component of a dynamic dataflow processor, the matching unit, has been identified as a major bottleneck. An alternative implementation for the matching unit is presented. This implementation increases the operating bandwidth of the unit by allowing token-matching operations to be done concurrently. The adoption of the proposed implementation also reveals throughput limitations of other units within the processor. As a result, a configuration for a dynamic dataflow processor is proposed that is believed to be cost-effective, to give high performance, and to be capable of incremental performance improvement.>