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Yanxiang Bi

dblp:287/4746 · DBLP profile ↗
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4ranked-venue papers
0as first author
4since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 2 · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 100%
Software engineering, system software, and programming languages
2 papers
Operating systems · 36% Program analysis · 36% Software testing · 28%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 66% Memory systems · 17% Interconnection networks and networks-on-chip · 17%

Topics — the 9 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › side-channel attack
contention-based side channels
0.912025
HubBub: Contention-Based Side-Channel Attacks on USB Hubs · USENIX Security Symposium 2025
Hardware security and side channels
side-channel attack
0.912025
HubBub: Contention-Based Side-Channel Attacks on USB Hubs · USENIX Security Symposium 2025
Hardware security and side channels
cache side channel
0.612022
MeshUp: Stateless Cache Side-channel Attack on CPU Mesh · SP 2022
Hardware security and side channels
microarchitectural side channel
0.612022
MeshUp: Stateless Cache Side-channel Attack on CPU Mesh · SP 2022
Program analysis
symbolic execution
0.512021
Boosting symbolic execution via constraint solving time prediction (experience paper) · ISSTA 2021
Software testing
test generation
0.512021
Boosting symbolic execution via constraint solving time prediction (experience paper) · ISSTA 2021
Memory systems
cache coherence
0.212022
MeshUp: Stateless Cache Side-channel Attack on CPU Mesh · SP 2022
Interconnection networks and networks-on-chip › network topology › mesh network
mesh topology
0.212022
MeshUp: Stateless Cache Side-channel Attack on CPU Mesh · SP 2022
Program analysis
constraint solving
0.112021
Boosting symbolic execution via constraint solving time prediction (experience paper) · ISSTA 2021

Methods — techniques the papers use, named apart from their topics

userspace bypass · 1.3contention analysis · 0.9machine learning · 0.5adaptive timeout prediction · 0.5
YearPublicationVenuePosition
2025 HubBub: Contention-Based Side-Channel Attacks on USB Hubs
Junpeng Wan, Yanxiang Bi, Jing (Dave) Tian
USENIX Security Symposium2
2023 Userspace Bypass: Accelerating Syscall-intensive Applications
Zhe Zhou 0001, Yanxiang Bi, Junpeng Wan, Zhou Li 0001
OSDI2
2022 MeshUp: Stateless Cache Side-channel Attack on CPU Mesh
abstract
Cache side-channel attacks lead to severe security threats to the settings where a CPU is shared across users, e.g., in the cloud. The majority of attacks rely on sensing the micro-architectural state changes made by victims, but this assumption can be invalidated by combining spatial (e.g., Intel CAT) and temporal isolation. In this work, we advance the state of cache side-channel attacks by showing stateless cache side-channel attacks on server-grade CPUs, that can bypass both spatial and temporal isolation. Unlike stateful cache side-channel attacks that rely on the timing difference between a cache hit or miss, our attack exploits the timing difference caused by the interconnect congestion. Specifically, to complete cache transactions, for Intel server CPUs, which use non-inclusive and mesh interconnect, cache lines would travel across cores via the CPU mesh and UPI interconnects. Nonetheless, the interconnects are shared by all cores, and cache isolation does not segregate the traffic. An attacker can generate traffic to contend with a victim on a link, measure the extra delay, deduce the memory access pattern of the victim’s program, and infer its sensitive data. Based on this idea, we implement MESHUP, a stateless cache side-channel against mesh interconnect, and test it against the existing RSA implementations of JDK for the cross-core attack and application fingerprinting for the the cross-CPU attack. We found the RSA private key used by a victim process can be partially recovered and the co-running application can be inferred at high accuracy.
Junpeng Wan, Yanxiang Bi, Zhe Zhou 0001, Zhou Li 0001
SP2
2021 Boosting symbolic execution via constraint solving time prediction (experience paper)
abstract
Symbolic execution is an essential approach for automated test case generation. However, the approach is generally not scalable to large programs. One critical reason is that the constraint solving problems in symbolic execution are generally hard. Consequently, the symbolic execution process may get stuck in solving such hard problems. To mitigate this issue, symbolic execution tools generally rely on a timeout threshold to terminate the solving. Such a timeout is generally set to a fixed, predefined value, e.g., five minutes in angr. Nevertheless, how to set a proper timeout is critical to the tool’s efficiency. This paper proposes an approach to tackle the problem by predicting the time required for solving a constraint model so that the symbolic execution engine could base on the information to determine whether to continue the current solving process. Due to the cost of the prediction itself, our approach triggers the predictor only when the solving time has exceeded a relatively small value. We have shown that such a predictor can achieve promising performance with several different machine learning models and datasets. By further employing an adaptive design, the predictor can achieve an F1-score ranging from 0.743 to 0.800 on these datasets. We then apply the predictor to eight programs and conduct simulation experiments. Results show that the efficiency of constraint solving for symbolic execution can be improved by 1.25x to 3x, depending on the distribution of the hardness of their constraint models.
Sicheng Luo, Hui Xu 0009, Yanxiang Bi, Xin Wang 0002, Yangfan Zhou 0002
ISSTA3