This paper presents a 14 GHz sub-sampling PLL (SSPLL) with its phase noise analysis for Ku-band wireless transceivers. The performance enhancement of the phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured results. The proposed capacitor multiplier reduces the size of the loop filter capacitor by 28 times. The active capacitor VCO decreases the out-band phase noise while consuming less power. Fabricated in a 65 nm CMOS process with a core active area of$0.0918~mm^{2}$, the SSPLL operates at 1.2 V supply achieving 13.2-14.8 GHz tuning range, 85.4 fs integrated jitter at 14 GHz, 8.42 mW power consumption, and −252.12 dB figure-of-merit (FoM). The measured results in-band and out-band phase noises of −108.6 dBc/Hz at a 1 MHz offset and −128.9 dBc/Hz at a 10 MHz offset, respectively.

Machine learning (ML) models have gained prominence in solving real-world tasks. However, implementing ML models is both compute- and memory-intensive. Domain-specific architectures such as Resistive Random Access Memory (ReRAM)-based Processing-in-Memory (PIM) platforms have been proposed to efficiently accelerate ML training and inference. However, existing ML workloads require a high amount of area and power for training. A major contributor to the area and power overheads is the Analog-to-Digital Converter (ADC). In this work, we propose a mixed pruning technique along with a novel reconfigurable ADC design to improve the power consumption profile. Overall, the pruned model with the reconfigurable ADC achieves ~50% reduction in power for training compared to existing state-of-the-art ReRAM-based architectures.

The best beam steering directions are estimated through beam training, which is one of the most important and challenging tasks in millimeter-wave and sub-terahertz communications. Novel array architectures and signal processing techniques are required to avoid prohibitive beam training overhead associated with large antenna arrays and narrow beams. In this work, we leverage recent developments in true-time-delay (TTD) arrays with large delay-bandwidth products to accelerate beam training using frequency-dependent probing beams. We propose and study two TTD architecture candidates, including analog and hybrid analog-digital arrays, that can facilitate beam training with only one wideband pilot. We also propose a suitable algorithm that requires a single pilot to achieve high-accuracy estimation of angle of arrival. The proposed array architectures are compared in terms of beam training requirements and performance, robustness to practical hardware impairments, and power consumption. The findings suggest that the analog and hybrid TTD arrays achieve a sub-degree beam alignment precision with 66% and 25% lower power consumption than a fully digital array, respectively. Our results yield important design trade-offs among the basic system parameters, power consumption, and accuracy of angle of arrival estimation in fast TTD beam training.