EDBT 2026 Demo / reviewers in the wild / expert
Raveesh Garg
dblp:287/9175
· DBLP profile ↗
3ranked-venue papers
2as first author
3since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Cello: Co-Designing Schedule and Hybrid Implicit/Explicit Buffer for Complex Tensor ReuseabstractTensor algebra accelerators have been gaining popularity for running high-performance computing (HPC) workloads. Identifying optimal schedules for individual tensor operations and designing hardware to run these schedules is an active area of research. Unfortunately, operators in HPC workloads such as Conjugate Gradient often have operators with skewed shapes, fundamentally limiting the reuse any schedule can leverage. Moreover, the operators form a complex DAG of dependencies, making it challenging to apply simple fusion/pipelining techniques to extract inter-operation reuse. To address these challenges, this work proposes an accelerator Cello. Cello uses a novel on-chip buffer mechanism called Chord co-designed with a novel scheduler called Score, which together enables identifying and exploiting reuse over complex DAGs of tensor operations. Cello provides 4x geomean speedup and 4x energy efficiency over state-of-the-art accelerators across HPC workloads. Raveesh Garg, Michael Pellauer, Sivasankaran Rajamanickam, Tushar Krishna |
IPDPS | 1 |
| 2023 | Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN ProcessingabstractSparsity is a growing trend in modern DNN models. Francisco Muñoz-Martínez, Raveesh Garg, Michael Pellauer, José L. Abellán, Manuel E. Acacio, Tushar Krishna |
ASPLOS (3) | 2 |
| 2022 | Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial AcceleratorsabstractGraph Neural Networks (GNNs) have garnered a lot of recent interest because of their success in learning representations from graph-structured data across several critical applications in cloud and HPC. Owing to their unique compute and memory characteristics that come from an interplay between dense and sparse phases of computations, the emergence of recon-figurable dataflow (aka spatial) accelerators offers promise for acceleration by mapping optimized dataflows (i.e., computation order and parallelism) for both phases. The goal of this work is to characterize and understand the design-space of dataflow choices for running GNNs on spatial accelerators in order for mappers or design-space exploration tools to optimize the dataflow based on the workload. Specifically, we propose a taxonomy to describe all possible choices for mapping the dense and sparse phases of GNN inference, spatially and temporally over a spatial accelerator, capturing both the intra-phase dataflow and the inter-phase (pipelined) dataflow. Using this taxonomy, we do deep-dives into the cost and benefits of several dataflows and perform case studies on implications of hardware parameters for dataflows and value of flexibility to support pipelined execution. Raveesh Garg, Eric Qin 0001, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain 0001, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna |
IPDPS | 1 |