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Feng-Ming Tsai

dblp:288/4115 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Hardware accelerators and domain-specific architectures · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.512021
Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration · DAC 2021
Hardware accelerators and domain-specific architectures
constraint satisfaction
0.512021
Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration · DAC 2021

Methods — techniques the papers use, named apart from their topics

trust-region method · 0.5supervised learning · 0.5model-based agent · 0.5feed-forward network · 0.5deep reinforcement learning · 0.5
YearPublicationVenuePosition
2021 Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration
abstract
This paper introduces new perspectives on analog design space search. To minimize the time-to-market, this endeavor better cast as constraint satisfaction problem than global optimization defined in prior arts. We incorporate model based agents, contrasted with model-free learning, to implement a trust-region strategy. As such, simple feed-forward networks can be trained with supervised learning, where the convergence is relatively trivial. Experiment results demonstrate orders of magnitude improvement on search iterations. Additionally, the unprecedented consideration of PVT conditions are accommodated. On circuits with TSMC 5/6nm process, our method achieve performance surpassing human designers. Furthermore, this framework is in production in industrial settings.
Kai-En Yang, Chia-Yu Tsai, Hung-Hao Shen, Chen-Feng Chiang, Feng-Ming Tsai, Chung-An Wang, Yiju Ting, Chia-Shun Yeh, Chin-Tang Lai
DAC5