Bora Bilgic

dblp:288/6094 · DBLP profile ↗
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3ranked-venue papers
2as first author
3since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2022 Guaranteed Activation of Capacitive Trojan Triggers During Post Production Test via Supply Pulsing
abstract
Involvement of many parties in the production of integrated circuits (ICs) makes the process more vulnerable to tampering. Consequently, IC security has become an important challenge to tackle. One of the threat models in hardware security domain is the insertion of unwanted and malicious hardware components, known as Hardware Trojans (HTs). A malicious attacker can insert a small modification into the functional circuit that can cause havoc in the field. To make the Trojan circuit stealthy, trigger circuits are typically used. The purpose of the trigger circuit is to hide the Trojan activity during post-production testing, and to randomize activation conditions, thereby making it very difficult to diagnose even after failures. Trigger mechanisms for Trojans typically delay and randomize the outcome based on a subset of internal digital signals. While there are many different ways of implementing the trigger mechanisms, charge based mechanisms have gained popularity due to their small size. In this paper, we propose a scheme to ensure that the trigger mechanisms are activated during production testing even if the conditions specified by the malicious attacker are not met. By disabling the mechanism that makes the Trojan stealthy, any of the parametric techniques can be used to detect Trojans at production time. The proposed technique relies on supply pulsing, where an increased potential difference between the gate and bulk of the active transistor in the output stage generates an alternate charge path for an otherwise unreachable capacitor and bypasses the input conditions to the trigger mechanism. SPICE simulations show that our method works well even for the smallest Trojan trigger mechanisms.
Bora Bilgic, Sule Ozev
DATE1
2022 Performance Degradation Monitoring for Analog Circuits Using Lightweight Built-in Components
abstract
The need for digital calibration due to large variations in fine-geometry processes as well as the need for performance locking mechanisms to prevent IC piracy have resulted in the prevalent use of digital assistance for analog circuits. The same issues also make analog circuits vulnerable to infield performance degradation either due to wearout or due to potential attacks by adversaries. Unfortunately, most of the vulnerabilities are activated after the device is deployed. In order to ensure secure and reliable operation of the system, abrupt performance fluctuations in analog circuits need to be detected in the field. The detection method needs to be robust with respect to process variations, low-cost, and avoid providing information that attackers can use to compromise the circuit. In this paper, we propose a simple method for detecting performance degradation of digitally-assisted analog circuits using simple circuit elements, such as level shifters and inverters. The proposed method identifies an easy-to-monitor invariant in the circuit that is correlated to performance variables but this correlation is not known to attackers. The proposed method is demonstrated on a low drop out voltage regulator (LDO). Experimental results confirm that the proposed method can detect deviations in performance due to the alteration of calibration or performance locking bits.
Bora Bilgic, Sule Ozev
VTS1
2022 Digital Fault-based Built-in Self-test and Evaluation of Low Dropout Voltage Regulators
abstract
With increasing pressure to obtain near-zero defect rates, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, power converters, and data converters. This article presents an extremely low-cost built-in self-test technique for LDOs, specifically designed for fault detection. The methodology relies on exciting the LDO loop at the voltage reference input via a pseudo-random signal with white noise characteristics and observing the response from the output of LDO via all-digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with an LDO as a device under test is designed in 65nm technology. Fault simulations performed at the transistor level show that all resistive open/short defects in circuit components can be detected even if they do not cause a catastrophic failure in the LDO response. The proposed technique is validated with hardware using off-the-shelf components.
Mehmet Ince, Bora Bilgic, Sule Ozev
ACM J. Emerg. Technol. Comput. Syst.2