Rubén Gómez-Merchán

dblp:288/9741 · DBLP profile ↗
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4ranked-venue papers
3as first author
4since 2021 · last 2025
0000-0003-4169-9682ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 4 since 2021
YearPublicationVenuePosition
2025 Dynamic Vision With Single Photon Detectors: A Discrete DVS Architecture Using Asynchronous Sensor Front-Ends
abstract
This paper reports an architectural concept for achieving dynamic vision with Single-Photon Avalanche Diode (SPAD) detectors. This new concept, demonstrated through a dedicated proof-of-concept sensor chip and an associated camera module, addresses the challenge of large data volume due to frequent laser exposures by optimizing data processing via temporal-contrast-based event filtering. The manuscript analyzes trade-offs between contrast sensitivity, latency, and noise in the proposed discrete DVS architecture and validates the proposal through experimental results obtained with the camera module. The proposed sensor has different operation modes that show potential for augmented reality applications. Benchmarking comparison with competing SPAD-based vision sensors shows latency and power consumption advantages.
Rubén Gómez-Merchán, Juan A. Leñero-Bardallo, Rafael de la Rosa-Vidal, Ángel Rodríguez-Vázquez
IEEE Trans. Circuits Syst. I Regul. Pap.1
2025 Event-Driven Vision Sensor With In-Pixel Spatial Contrast Computation Capabilities and On-Chip AER Sequencer
abstract
Spatial contrast (SC) detection is a fundamental task in computer vision, crucial for simplifying images at an early stage. However, this process typically demands significant power and processing resources. In this paper, we present a novel 128 × 128 pixel asynchronous vision sensor designed to compute SC, thereby eliminating the need to transmit and process intensity frames externally. The sensor is fabricated using 180 nm CMOS technology, with a pixel pitch of$28 \times 26 \mu \text {m}^{2}$. Each pixel provides temporal information relative to its four adjacent pixels to compute the temporal contrast, transmitting data asynchronously. An integrated on-chip Address-Event-Representation (AER) sequencer efficiently manages pixel events, reducing latency requirements on the processing unit. Additionally, the sensor is capable of performing standard imaging operations. Various methods for SC computation are discussed, along with their implementation within the sensor.
Rafael de la Rosa-Vidal, Juan A. Leñero-Bardallo, Rubén Gómez-Merchán, Ángel Rodríguez-Vázquez
IEEE Trans. Circuits Syst. I Regul. Pap.3
2024 A Discrete Approach to Dynamic Vision with Single-Photon Detectors
abstract
This paper presents a novel approach to implement discrete dynamic vision utilizing Single-Photon Avalanche Diode (SPAD) detectors. Departing from conventional continuous-time methodologies, our approach encodes photon arrival rates into frequency-based spikes, enabling asynchronous event-driven processing. The theoretical framework is validated through experimental results. Probability models for event detection and background noise are developed, demonstrating excellent agreement with theoretical predictions. The proposed probability models serve as a key tool for analyzing trade-offs between contrast sensitivity, speed, and background noise. This work not only advances the field of dynamic vision but also lays the groundwork for further innovations in SPAD-based imaging technologies.
Rubén Gómez-Merchán, Juan A. Leñero-Bardallo, Pablo Fernández-Peramo, Ángel Rodríguez-Vázquez
ISCAS1
2023 Load Reduction and Adaptive Pull-Up Strategies for Time Delay Reduction in High-Resolution AER Sensors
abstract
The Address Event Representation (AER) protocol is widely used in pixelated neuromorphic systems to implement word-serial asynchronous transmission links. The data is encoded in time or frequency and transferred from the pixel to the receiver in the form of events through a shared channel. Asynchronous sensors benefit from lower data throughput, power consumption, and latency; however, they present several timing limitations to scale the size of the array, since delay in the transmission line and collisions in the readout channel corrupt the timing information. This paper analyzes the effect of increasing the number of pixels in terms of transmission delay and proposes several design guidelines to overcome scaling limitations in high-resolution pixel arrays. The results of the post-layout simulation verify the effectiveness of the design proposals, achieving a reduction of more than 70% in the time delay of the request line.
Rubén Gómez-Merchán, Rafael de la Rosa-Vidal, Juan A. Leñero-Bardallo, Ángel Rodríguez-Vázquez
ISCAS1