Demo Data from EDBT 2026 / reviewers in the wild / expert
Amit Tiwari
dblp:289/2709
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › synchronization
barrier synchronization |
0.9 | 1 | 2025 | Unleashing Parallelism with Elastic-Barriers · ACM Trans. Archit. Code Optim. 2025 |
Parallel and multicore computing
load balancing |
0.9 | 1 | 2025 | Unleashing Parallelism with Elastic-Barriers · ACM Trans. Archit. Code Optim. 2025 |
Parallel and multicore computing
synchronization |
0.9 | 1 | 2025 | Unleashing Parallelism with Elastic-Barriers · ACM Trans. Archit. Code Optim. 2025 |
Compilers and program optimization
parallelizing compiler |
0.3 | 1 | 2025 | Unleashing Parallelism with Elastic-Barriers · ACM Trans. Archit. Code Optim. 2025 |
Methods — techniques the papers use, named apart from their topics
compile-time and runtime optimization · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Unleashing Parallelism with Elastic-BarriersabstractWith the rise of multi-core processors, parallel programming has become essential, and managing synchronization overheads has become crucial for efficiency. Barriers, commonly used to synchronize threads, divide the program into different phases. Existing scheduling schemes address intra-phase load imbalance to some extent but do not fully resolve the issue of thread idling, especially in the context of programs with irregular parallel for-loops. This article proposes an innovative solution called the elastic-barrier , where threads that arrive early at a barrier can execute iterations of the parallel-loop from the next phase, thereby reducing the idle time, and reduce load imbalance. The approach guarantees safety by ensuring that before executing any work W from the subsequent phase, all the works in the current phase that W depends on have been executed. The article presents a compilation scheme that integrates compile-time and runtime techniques to optimize execution. We implemented our proposed scheme in the IMOP framework. Experimental results on graph-based benchmarks show that our approach improves the performance significantly. Amit Tiwari, V. Krishna Nandivada |
ACM Trans. Archit. Code Optim. | 1 |
| 2021 | Evaluation and analysis of Data Management Plan tools: A parametric approach
Sagar Bhimrao Gajbe, Amit Tiwari, Gopalji |
Inf. Process. Manag. | 2 |