The evolution towards software-defined vehicles and the intense computational demands of artificial intelligence (AI) are driving the automotive industry to adopt heterogeneous, chiplet-based compute architectures. This paradigm shift is propelled by the need for scalable performance across vehicle models, faster innovation cycles, and cost-effective integration of specialized functions. While this approach offers significant design flexibility, it introduces two fundamental challenges: 1) the complex and time-consuming task of evaluating the performance of countless possible chiplet configurations, and 2) the need to efficiently map and optimize AI inference workloads onto diverse hardware accelerators. This paper addresses both issues. We first detail the requirements for a rapid simulation methodology, emphasizing the need for an open, unified application programming interface (API) that allows for interchangeable hardware models from various vendors. We then demonstrate a hardware-aware AI inference optimization toolchain capable of targeting a wide range of accelerators, ensuring workload portability and performance. By combining these methodologies for rapid evaluation and targeted optimization, we establish a critical pathway for realizing the full potential of high-performance chiplet systems in next-generation vehicles.

Temporal isolation is one of the key challenges for co-running mixed-criticality applications on Commercial Off-The-Shelf (COTS) multi-core platforms. In particular, the main memory subsystem is one of the most prominent causes of interference and loss of isolation. Existing mechanisms for memory bandwidth regulation are limited to conservative bandwidth reservation, use pessimistic worst-case execution time (WCET) estimations or require dedicated hardware that is not feasible in COTS multi-core platforms.In this paper, we propose a novel mechanism for memory interference control that uses feedback-based control to dynamically regulate memory accesses of individual cores in a multicore platform. Our mechanism directly regulates the source of interference by leveraging information about memory utilization, acquired from existing hardware performance counters provided by modern COTS-based memory controllers. The proposed solution is implemented on Linux as a loadable kernel module. The results of evaluating our approach with real and synthetic benchmarks on a COTS multi-core (NXP S32V234) platform demonstrate that it is able to provide temporal isolation with up to 4x and 2x more overall throughput for non-real-time applications compared to static and dynamic memory bandwidth-based regulation approaches, respectively, while maintaining guarantees for applications running on the real-time core.

Due to the trends of centralizing the EIE architecture and new computing-intensive applications, high-performance hardware platforms are currently finding their way into automotive systems. However, the Systems-on-Chip (SoCs) currently available on the market have significant weaknesses when it comes to providing predictable performance for time-critical applications. The main reason for this is that these platforms are optimized for average-case performance. This shortcoming represents one major risk in the development of current and future automotive systems. In this paper we describe how highperformance and predictability could (and should) be reconciled in future HW /SW platforms. We believe that this goal can only be reached via a close collaboration among system suppliers, IP providers, semiconductor companies, and OS/hypervisor vendors. Furthermore, academic input will be needed to solve remaining challenges and to further improve initial solutions.