The reconstruction of signals using reconstruction algorithms is the most critical step in compressed sensing (CS) theory. In practical application scenarios, the sparsity of the signal is often unknown, which requires reconstruction algorithms to operate under sparsity-adaptive conditions. Existing sparsity adaptive algorithms have various limitations, and no algorithm has demonstrated good reconstruction performance in noisy real-world environments. This article fully considers reconstruction accuracy, robustness, and hardware complexity and proposes a sparsity adaptive atomic correlation difference pursuit (SA-ACDP) algorithm to achieve a balance among reconstruction accuracy, robustness, and hardware complexity. Experimental results show that the SA-ACDP algorithm achieves better reconstruction success rate (SR) compared with the existing sparsity adaptive algorithms and comparable reconstruction SR to existing algorithms with prior sparsity knowledge. It also exhibits better robustness and lower hardware complexity compared to existing algorithms. A hardware architecture applying the SA-ACDP algorithm is designed and implemented on a Virtex UltraScale+ FPGA with matrix dimension$= 1024\times 256$, maximum sparsity$K_{\max }= 128$. The proposed architecture achieves a reconstruction signal-to-noise ratio (RSNR) of 35.11 dB for random signals and 28.3 dB for ECG signals, with 18-bits data width and 13-bits fractional width. The maximum clock frequency of the architecture is 200 MHz, enabling reconstruction within$231~\mu $s. The proposed architecture achieves a dynamic power consumption of 2393 mW.

To alleviate the high energy consumption during the switching processing of capacitive digital to analog converter (CDAC) in successive approximation register analog-to-digital converters (SAR ADCs), this letter proposes a novel switching scheme. Based on the operation of voltage level shifting, decisions for the most significant bit (MSB) and the second MSB (2nd MSB) do not dissipate any energy. Subsequent decisions combine the advantages of monotonic and Vcm-based switching schemes, requiring only a single capacitor switch for each bit, simultaneously reducing the reference voltage shifting by half. The proposed switching scheme reduces capacitance distribution from “20C, …, 2N-1C” to “20C, …, 2N-3C,” which reduces the capacitance spread and thereby relaxes the capacitor matching requirements. Simulation results shows the reduction of switching energy consumption by 97.7%, and area saving by 75.0%. The proposed switching scheme is exploited in a prototype 10-bit, 20-KS/s SAR ADC. Measurements show an effective number of bits (ENOB) of 9.26 bits, a spurious-free dynamic range (SFDR) of 70.4 dB, and a power consumption of 45 nW, with CDAC energy at 10.8 nW.

This work presents a 10-bit 20-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a proposed single-capacitor switching scheme. Based on behavioral-level simulations and prototype chip testing, ultralow-power operation and significant chip area reduction are achieved. This novel switching scheme employs voltage level shifting instead of charge redistribution for the two most significant bit (MSB) decisions, thus eliminating switching power consumption. For the remaining bit decision, the technique minimizes reference voltage transitions while involving only a single capacitor in each switching. By employing the proposed switching scheme, the capacitance spread of capacitive digital-to-analog converter (CDAC) is reduced from conventional$2^{n-1}$to$2^{n-3}$, which reduces the CDAC area, relaxes capacitor matching requirements, and improves matching linearity. A prototype of the proposed ADC was designed and fabricated in SMIC 180-nm CMOS technology. The chip operates with a 0.6-V supply voltage and consumes 45-nW power at a sampling rate of 20 kS/s. The measurement results also show the signal-to-noise and distortion ratio (SNDR) of 56.4 dB, the spurious-free dynamic range (SFDR) of 70.4 dB, and the ENOB of 9.26 are achieved. The ADC occupies an area of only 0.063 mm2and attains the Walden figure of merit of 5.06 fJ/conversion-step at the Nyquist rate.

Reconstruction algorithms are an integral part of compressed sensing (CS) theory, which can reliably reconstruct the original signal from the low-dimensional compressed signal. The orthogonal matching pursuit (OMP) algorithm has been widely studied and extensively selected in hardware implementations. However, the low reconstruction success rate of the OMP algorithm under high sparsity conditions has led to the proposal and application of more reconstruction algorithms in hardware implementations. In this article, a staged projection refining multiple OMP (SPR-MOMP) algorithm is proposed based on the OMP algorithm. This algorithm improves the reconstruction accuracy by refining the support set using a staged backtracking strategy. It also employs a multiple-atom selection strategy for parallel expansion of the support set, ensuring reconstruction efficiency. The reconstruction simulation demonstrates that the SPR-MOMP algorithm achieves a higher reconstruction success rate than the OMP algorithm, with fewer iterations. A hardware architecture applying the SPR-MOMP algorithm is designed and implemented on a Virtex UltraScale+ field-programmable gate array (FPGA) with$N =1024$,$M =256$, and$K =36$. The proposed architecture achieves a reconstruction signal-to-noise ratio (RSNR) of 44.27 dB, with 20-bit data width and 15-bit fractional width. The maximum clock frequency of the architecture is 200 MHz, enabling reconstruction within$276.6~\mu $s. The proposed architecture achieves a lower dynamic power consumption of 1929 mW.

A flipped voltage follower (FVF)-based capacitor-less low-dropout (LDO) regulator is presented that features a fast transient response. The adaptive zero compensation is proposed to solve the full-load-range stability issue associated with the FVF LDO regulator. The presented FVF LDO regulator has been implemented in a 0.18 μm CMOS process with an active area of 0.026 mm2. The simulated loop phase margin exceeds 45° for the entire load range of 0-40 mA. The minimum power supply rejection of 56 dB at 1 MHz has been measured at the maximum load current of 40 mA. The measured transient response time is 0.48 ns over the load current range with a dynamic quiescent current of 36 to 76 μA, which results in a figure of merit among the best reported in recent publications.