The Planar Package Planner is a design aid aimed at helping to form a package layout plan, given only the information available during project initiation to digital system logic and package designers. A hierarchical approach is adopted, and a clustering program makes possible use of the layout scheme for bottom-up as well as top-down design. The layout plan for an experimental microprocessor is worked out as an example of the method.

A fresh look at the technical problems of present-day logic design and at the principal activities of the logic designer resulted in a system for hierarchical logic design. It is supported by a novel, high-level graphic language to describe the connections between logical devices. A major concern was to ensure that processes invoked by a user while designing, modifying and testing logic normally require only a few seconds or, on rare occasions, a few minutes to execute.

A logic design whose structure has the form of a hierarchy is easily verified in a conversational environment. The verification process is based on an explicit methodology, supported by appropriate utilities. The paper describes the verification of the experimental Josephson signal processor control logic by means of the ALEX logic design system.

This paper describes a method whereby multiple regression techniques are used to predict the delay between input and output signals through a combinatorial logic chain.

This paper describes an approach to the maintenance problem of central processors which minimizes the human role. This approach consists of a combination of 1) a programming system which computes the diagnostic program from the design-automation tape, and 2) a novel organization of a part of the controls of an experimental computer. Problems which require solution are listed and reasons are given as to why they were solved by the methods described. An account of the programming system and hardware as implemented is given, and improvements in them are considered in the light of difficulties encountered.