This paper presents an adversarial jamming attack detection method using energy-detection-based hardware for wireless Internet of Things (IoT) systems. The proposed method utilizes accurate RF signal energy level detection to establish a learning baseline for identifying different types of jamming attacks in wireless networks, which are often characterized by changes in RF energy levels. An adaptive threshold-based binary classification algorithm is implemented to use the detected signal’s energy level as the classification metric. This enables the detection of deceptive/reactive and periodic jamming attacks. Energy levels of RF signal are measured using an ultra-low power (ULP) direct RF-to-digital Received Signal Strength Indicator (RSSI) circuit, developed in a 65-nm CMOS technology, which consumes only 6 nW of power. Further, the RSSI circuit incorporates a band-pass response to filter out ambient signal in the network, providing resilience against continuous RF jammers. Furthermore, a system-level model of the proposed method is presented to demonstrate its detection capabilities. To mitigate the stochastic effects of the wireless channel, a minimum mean-square error (MMSE) channel equalizer is integrated, which improves the detection accuracy by reducing the attack detection error by 21.6%. The RF transmission packet structure is modeled based on the IEEE 802.15.4 protocol. We conducted extensive over-the-air measurements under various attack modalities and scenarios using universal software radio peripheral (USRP) B210 software defined radios (SDRs) to validate the detection accuracy of our proposed hardware-based detection method for energy-constrained IoT systems at 915 MHz. Measurement results demonstrate an accuracy of 96.4% for detecting deceptive jammer and periodic jammer, closely aligning with the simulation results.

This paper presents a high-efficiency, ultra-low-power automated on/off adaptive MPPT (AOA-MPPT) system for microscale energy harvesters. It is designed to extract the maximum available power from photovoltaic (PV), radio frequency (RF), and thermoelectric generator (TEG) energy sources. AOA-MPPT combines a power-change detector (PCD) that activates tracking only when input power changes (auto-on) with an auto-off convergence detector that halts perturbation at lock and powers down MPPT circuitry, eliminating steady-state dither and lowering controller power. Input power is estimated from a single sample of the inductor peak current, enabling duty-cycled sensing with low sensitivity to converter gain. A low-power, wide-range PWM control (LS-PWM) provides broad duty-cycle adjustment of the inductor charge time, enabling input impedance matching for maximum power transfer. The AOA-MPPT circuit is designed along with a boost converter and fabricated in 65nm CMOS technology. It achieves a peak tracking efficiency of 99.9%, a peak converter efficiency of 87%, and a power consumption of only 112nW.

K-means clustering algorithm partitions data into k unique and non-overlapping sets. Although the method primarily uses Euclidean distance, dissimilarity within datasets can be assessed using a variety of metrics. This paper focuses on assessing the performance of the K-means clustering algorithm using three distinct distance metrics: (i) Euclidean distance(L22norm), (ii) A proposed circuit design distance metric, and (iii) Manhattan distance(L2norm). However, integrating this type of functionality within a traditional CMOS design demands expensive hardware and results in considerable power consumption. The design’s performance was assessed using a standard K-means clustering algorithm with K=4 on the "Iris flower dataset". Findings indicate a classification throughput of 500 ns and a power consumption below 1 μW, achieving significantly lower energy consumption compared to a conventional digital CMOS design in 65 nm commercial CMOS technology.

Analog circuits remain vulnerable to different types of supply chain attacks including piracy, overproduction, counterfeiting, and reverse engineering. In this article, we present switch mode time domain locking (SMDL) technique to protect analog circuits. This technique integrates a locking mechanism into the time-domain functionality of the circuit. It uses random-key-based switching phases for analog circuits instead of fixed clocks that are conventionally used. The random switching phases are dependent on a key which can be made arbitrarily long. A correct key (CK) with correct alignment of phases can unlock circuit functionality. The locking technique can be applied to a variety of switch-mode analog circuits such as filters, amplifiers, regulators, among others. We implemented this technique on a folded cascode amplifier (FCA) and on a switched-capacitor bandgap reference (BGR) circuit. In both techniques, we employ a 128-bit key to lock the circuit functionality. The design is implemented in a 65-nm CMOS technology. An incorrect key (IK) introduces almost 100% variation in the circuit functionality, ensuring high level of security.

This article presents a closed-loop frequency and phase correction technique for distributed beamforming to maximize the wireless radio frequency (RF) power transfer from multiple energy transmitters (TX) to an Internet of Things (IoT) device receiver (RX). A mathematical analysis of the received power loss due to frequency and phase offset that exists between the transmitters, is used to establish a design methodology for frequency and phase correction among the n-transmitters. Our analysis quantifies the received signal power in the presence of frequency and phase offsets and shows that an optimal frequency and phase correction can boost the combined signal strength by a factor of$n^{2}$from n-transmitters. Further, we present optimal conditions which can expedite the phase offset correction implemented using the one-shot phase correction algorithm. Finally, we validate our frequency and phase offset correction technique to demonstrate a 9.5 dB improvement in received power from three transmitters using universal software radio peripheral (USRP) devices and commercial rectifier at 2.4 GHz for a distance of 3.3 feet between TX and RX. Our proposed closed-loop correction technique utilizes backscatter communication between TX and RX, which improves the energy efficiency of the distributed beamforming system.

Cognitive communication utilizes transient openings in the spectrum to communicate opportunistically, which is a promising technique to enable more efficient spectrum usage in an increasingly congested spectrum environment. We aim to address two main challenges associated with cognitive communication: (i) spectrum sensing should be fast and energy efficient for processing a large bandwidth in a short time; (ii) the spectrum sensing approach should be able to simultaneously recognize multiple signals that are present. In this paper, we propose to address these challenges with a novel design framework that consists of a fast on-chip spectrum sensing in conjunction with a novel learning-based spectrum analysis model at the edge to enhance the optimizations for spectrum agility. We first utilize a model of a programmable analog-based high-quality factor (Q) on-chip spectrum sensor that is capable of scanning the sub-6 GHz band to detect the spectrum usage in less than 1μs. The proposed spectrum sensor also enhances the energy efficiency of the sensing. To complement the onchip spectrum sensor, a deep learning (DL) model is deployed for a fine-grained signal detection between channels in the 400 MHz to 6 GHz range, which is intended to be executed on edge devices. Simulation results show that the DL model can detect multiple different modulated signals with a mean Intersection-over-Union (IoU) of 86.8% in highly-variable bandwidth and center frequency scenarios. Finally, we present a system-level model of our framework to demonstrate the spectrum sensing and classification in the sub-6 GHz frequency band.

Side channel attacks (SCA) have been shown to be very effective in breaking cryptographic engines. In this paper, we present a new power obfuscation switched capacitor (POSC) DC-DC converter. To a first order approximation, it equalizes the charge such that the same amount of charge is drawn from the input power supply in each cycle. We evaluated the design by analyzing the power supply to an Advanced Encryption Standard (AES) unit powered by the proposed converter. CPA fails after evaluation with 10k traces. Two different topologies of the switched capacitor circuit are analyzed for their contribution to side channel power information leakage. The three phase POSC is designed with both switched capacitor converters (SCC1 and SCC2) and achieves efficiency of 77% and 70%.

This paper presents a chopper instrumentation amplifier (IA) architecture with two symmetric differential negative capacitance generation feedback (NCGFB) loops. The NCGFB design technique enables to cancel parasitic capacitances of cables and electrodes at the IA input in order to boost the input impedance. The negative capacitance is generated through feedback loops containing digitally programmable capacitor banks that can compensate for an extra input capacitance of up to 100 pF. A chopping technique is also introduced to enhance the noise performance of NCGFB IAs with input impedance boosting. The proposed amplifier is based on the capacitively-coupled IA (CCIA) architecture with additional circuit-level innovations to increase input impedance and improve noise performance. Two NCGFB loops have been added to further boost the input impedance. These NCGFB loops include a low-pass filter (LPF) to suppress ripples from the chopping prior to feeding the signal back to nodes at which capacitances are cancelled. We present an analysis to verify the stability of the loops as well as their effects on boosting the input impedance. The full symmetry of the NCGFB loops enables the use of identical capacitor banks to maintain a high common-mode rejection ratio (CMRR). The IA was designed and fabricated in 65-nm CMOS technology with a 1.2V supply and consumes$2.46~\mu $W. Chip measurements show that the IA has a 44-dB gain, 40-Hz bandwidth, a total harmonic distortion (THD) of −44.3 dB with 35 mVpp sinusoidal output at 10 Hz, CMRR >90.9 dB, a 92.3 dB power supply rejection ratio (PSRR), 0.54-$\mu $V integrated input-referred noise over a bandwidth of 0.5 - 40 Hz with a noise efficiency factor of 4.75, and an input impedance of 1.9 G$\Omega $at 10 Hz even with an extra input capacitance of 100 pF.

This paper presents a maximum power point tracking (MPPT) circuit for DC-DC converters which is well suited for DC energy harvesters. To save the power of the tracking circuit when there is no variation in the input power, a power change detector (PCD) circuit is also proposed in the MPPT circuit. With PCD, changes in the input power are detected, thereby activating the MPPT circuitry for tracking. When MPP is achieved, the proposed logic shuts down the MPPT-related circuits to save power. A modified hill-climbing (HC) technique is implemented for the tracking algorithm to address the speed/precision tradeoff. The MPPT circuit uses a power estimation method based on sensing and sampling of the inductor peak current, achieving a high tracking efficiency. The proposed MPPT system is designed in 65nm CMOS technology. Simulation shows a peak tracking efficiency (TE) of 99.9% is achieved without oscillation of the operating point. The power consumption of the proposed MPPT circuit is 125nW.

In this work, we propose a passive radio frequency (RF) front-end tailored for wake-up receivers (WuRx) to be deployed in cellular Internet of Things (IoT) devices and wearables networks, featuring a low radiation resistance antenna and a high-$Q$matching network implemented with microacoustic resonators integrated to obtain a systematic higher node’s sensitivity at no cost in terms of power consumption. We show how these components can be co-designed to obtain high passive voltage gain, hardware-level blocker immunity, and increased resilience to integration parasitics, relaxing link budget for low-power IoT nodes. We report experimental validation of a PCB antenna with 2-dBi gain measured on an 11-$\Omega $input resistance at resonance, and an in-house fabricated micro-electro-mechanical system (MEMS) thin-film aluminum nitride bulk acoustic resonator with a quality factor$Q=550$and a piezoelectric coupling coefficient$k_{t}^{2} = \mathrm {7~ \%}$, hybridly integrated with a commercial off-the-shelf low-power WuRx circuit to benchmark the proposed RF front-end design at 850 MHz. We demonstrate a passive voltage gain of 12 dB due to the MEMS resonator, and an additional 11 dB due to the proposed antenna design (for a total of an unprecedented 2-dB passive gain in this frequency range) leading to an over the air −61-dBm minimum detectable input power and 23-dB blocker rejection.

This article presents a design approach for the modeling and simulation of ultralow power (ULP) analog computing machine learning (ML) circuits for seizure detection using electroencephalography (EEG) signals in wearable health monitoring applications. In this article, we describe a new analog system modeling and simulation technique to associate power consumption, noise, linearity, and other critical performance parameters of analog circuits with the classification accuracy of a given ML network, which allows to realize a power and performance optimized analog ML hardware implementation based on diverse application-specific needs. We carried out circuit simulations to obtain nonidealities, which are then mathematically modeled for an accurate mapping. We have modeled noise, nonlinearity, resolution, and process variations such that the model can accurately obtain the classification accuracy of the analog computing-based seizure detection system. Noise has been modeled as an input-referred white noise that can be directly added at the input. Device process and temperature variations were modeled as random fluctuations in circuit parameters, such as gain and cut-off frequency. Nonlinearity was mathematically modeled as a power series. The combined system level model was then simulated for classification accuracy assessments. The design approach helps to optimize power and area during the development of tailored analog circuits for ML networks with the ability to potentially trade power and performance goals while still ensuring the required classification accuracy. The simulation technique also enables to determine target specifications for each circuit block in the analog computing hardware. This is achieved by developing the ML hardware model, and investigating the effect of circuit nonidealities on classification accuracy. Simulation of an analog computing EEG seizure detection block shows a classification accuracy of 91%. The proposed modeling approach will significantly reduce design time and complexity of large analog computing systems. Two feature extraction approaches are also compared for an analog computing architecture.

This paper presents a temperature compensated RC oscillator (TC-RCO) designed in 130 nm CMOS technology using regular$V_{TH}$transistors. The TC-RCO uses constant transconductance ($g_{m}$) biasing for first order temperature compensation. Device mismatch based offset correction and delay compensation techniques in the comparator are used to improve temperature instability by cancelling out second order effects. The oscillator achieves a minimum temperature stability down to 21 ppm/° C for a temperature range of −20 to$100 ^{\circ} \text{C}$. In the lowest power mode, the oscillator consumes 254 nW power from a 1 V supply. The TC-RCO is operated in two modes, a low power mode that consumes an average of 254 nW and a high stability mode that consumes an average of 345 nW. A duty-cycling technique is used to correct offset after four cycles of oscillation. The oscillator exhibits long term stability of 10 ppm after 1 s integration time.

Emerging Analog Trojans such as A2, large-delay Trojans, and row-hammer have been shown to be more stealthier than previously known digital Trojans. They are smaller sized, do not rely on inputs for triggering, and the trigger for their payload can be made arbitrarily delayed, like a ticking time bomb. Furthermore, analog Trojans can easily evade detection due to their novel nature and incompatibility with the digital design and validation flow. In this paper, we propose a current signature-based detection scheme, which can effectively catch various analog Trojans at both run-time and production time validation. The paper includes techniques that advance Trojan detection method through incorporating detection of transient variation in the power supply current. Proposed current-sensor can sense currents down to 10s of nano-Amps improving over prior power sensing based techniques. Further, a configurable design of current sensor is developed to enable large range sensing capability. The design is also developed to be compatible with the digital design flow and can be logic obfuscated. This detection method can be used at run-time to potentially fence off activation of analog Trojans in the field through early warning signals. The commercial 65nm CMOS technology is utilized to verify the proposed idea.

This paper presents a new technique of radio frequency (RF) signal strength detection with a received signal strength indicator (RSSI) circuit which can be deployed in an internet-of-things (IoT) network. The proposed RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier's output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit is used to correct detection inaccuracies. The RSSI circuit is implemented in a 65-nm CMOS process and consumes 6nW power. It has a linear dynamic range of 26dB and exhibits an error of ±0.5dB with a wide bandwidth of 750MHz. A detailed analysis of the RSSI circuit is presented and verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of our RSSI circuit is favourable for IoT applications including localization, beamforming, hardware security and other low-power applications.

This article presents large delay-based analog Trojan circuits, a new class of analog Trojans that can be interfaced with digital and analog macros to launch fabrication-time hardware attacks. Two different circuit topologies of analog Trojan are presented, which can generate a delayed trigger output after two days and 60 ms, respectively, when implemented in 65-nm CMOS technology. The large delay is achieved using the transistor's gate-oxide leakage current or a diode's reverse saturation current in combination with the Miller capacitance-based circuits. The proposed analog Trojans can operate across multiple on-chip power domains and can be launched without any digital input signal, making their detection challenging. They show very limited variation in side-channel parameters, which makes them harder to detect through side-channel analysis. In addition, the proposed designs have a small area footprint of 55.5 μm2and 28 μm2, respectively, and can be easily concealed on-chip. We also demonstrate an attack launched using these Trojans to construct a “kill-switch” that disables the power management unit of an IC. Process and temperature variations were also investigated to assess their impact on the design. We implemented the thick-oxide gate leakage modeling to study the robustness of the proposed Trojan design. We also present the long-term potential threat of these Trojans where the output trigger signal is generated after an even larger delay.

This paper presents a high efficiency DC-DC converter architecture with adjustable switching frequency to suppress the baseband noise from a power supply for an RF receiver front-end. The system is composed of a boost converter operating in a discontinuous conduction mode (DCM), an analog frequency-to-voltage converter (FVC), and a digital control loop. To prevent the switching noise of the power supply from mixing into the intermediate frequency (IF) signal band of the mixer, the FVC senses the switching frequency of a boost converter and compares it with a reference baseband frequency. The digital control scheme changes the switching frequency of the boost converter if it is close to the baseband frequency by increasing the bias current of the regulating comparator. The complete system has been designed in a 0.13 μm CMOS process. The simulated efficiency of the boost converter is 84.5% with a 300mV input level. Its peak inductor current control has been designed for different input voltage conditions ranging from 50mV to 300mV. The output voltage of the boost converter is 1V with a 1.35% ripple. The converter was simulated with an RF mixer circuit as load, where the mixer achieved an SFDR of 60.3 dB.

Advances of machine learning algorithms have led to improvements of seizure detection capabilities in monitoring systems based on electroencephalography (EEG). Seizure detection hardware requires accurate feature extraction, which is conventionally done in the digital domain by extracting power in different EEG frequency bands over a particular time window. This paper presents an analog counterpart to digital feature extraction. A received signal strength indicator (RSSI) circuit is used for extracting EEG power features in the analog domain. A high-precision RSSI circuit was designed in the sub-threshold domain with ultra-low power consumption and low sensitivity to process-voltage-temperature variations with CMOS technology. Simulation results show that the RSSI circuit consumes 24 nW power, and has a dynamic range of 53 dB with a linearity error of ± 0.5 dB, sufficient to accurately extract features for seizure classification. The analysis of 16 hours of patient EEG data indicates a seizure classification accuracy of 94%, and a non-seizure classification of 86%.

This paper studies the effects of DC-DC switching converters on RF and analog baseband circuits. Simulations of a low-noise amplifier, mixer, and lowpass filter have shown that the impact of switching supply noise can be kept to small levels by design. For the case of loads with frequency conversion, a boost converter design technique to shift the switching frequency of the converter out of the band of interest is proposed.

This paper presents the design of an ultra-low power subthreshold Gm stage where transconductance is very stable with process, temperature, and voltage variations. This technique is used to design a differential amplifier with constant gain and a second order biquad filter with constant cut off frequency. The amplifier gain achieves a small temperature coefficient of 48.6 ppm/°C and exhibits small sigma of 75 mdB with process. The second order biquad achieves temperature stability of 69 ppm/°C and a voltage coefficient of only 49 ppm/mV.

This paper presents a charge-pump based low swing interconnect receiver circuit. The interconnect circuit is single ended and supports swings of 300mV or lower. A charge pump front end at the receiver boosts the arriving signal before restoring it to the full logic level, improving the performance of the interconnect. For a 10mm long interconnect wire in a 45nm CMOS process, the proposed scheme provides 3X energy reduction at constant speed and 3.5X delay improvement at constant energy relative to prior art. We deploy the interconnect scheme as the data bus between the L1-L2 caches of a 4-core Alpha processor. Over a set of Splash benchmarks, the proposed architecture reduces total energy consumption by 70% while maintaining the same performance.