Execution times of FPGA streaming architectures implementing large DFGs with large datasets, as in mesh-based CFD simulations, mostly depend on the long data transfers between external memory and FPGA. If datasets consist of variable-length data packets (i.e. describing unstructured meshes), the common approach that forces the longest length in all packets to facilitate stream decoding decreases overall performance due to the increased size of the stream. This paper presents the design of a parameterizable high-performance decoder of variable-length packets. It uses a general data frame structure and it enhances performance through optimized pipelined computations and distributed flow control. Results show working frequencies over 400~MHz on a Stratix V device, improving performance by at least 45% from a previous ad-hoc design.

Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are commonplace in resource, latency, or power constrained designs. This paper describes and proves correct a formal method for accurate high-level casting of optimal adders and subtractors. The proposed approach allows for an early accurate estimation of resource usage which is then available for high-level decision-taking in the design flow. As a result, decoupling between high-level and low-level synthesis is achieved. Results concerning the impact of the approach on resource estimates and a discussion on the wide applicability of the method are presented.

Power models are at the heart of high-level estimation methods used for industrial power evaluation of FPGA-based electronic designs. In this paper, probabilistic power estimation models of binary divider IP cores implemented in reconfigurable logic are presented. The models are ready for use at the algorithmic and RTL levels of the design flow and are simulation-independent, thus resulting in fast estimation times. The only parameters the model needs are the bit-widths of the operator inputs and their signal statistics: mean values, variances and autocorrelation coefficients. Based on these parameters and taking into account the particular logic structure of the binary divider cores, analytical probabilistic formulas are used to calculate the overall switching activity in the circuits-the main cause of dynamic power consumption. Estimates are compared with both real on-board measurements and estimates from the simulation-based tool XPower from Xilinx. Results show that the mean relative estimation errors are within 10% of on-board measurements or low-level estimates, and the average time to obtain power estimates using the proposed models is only 135 ms.

We present a methodology for power estimation of non-fractional divider cores implemented in FPGAs. The methodology takes into account the divider structure and the signal statistics at the inputs: mean, variance, and autocorrelation. An analytical model is used for switching activity computation. The strong data dependency observed at the inputs of the divider basic elements is properly modelled in order to improve the model accuracy. The methodology is capable of obtaining fast and accurate estimates when compared to both, real on-board measurements and XPower. The mean relative error is less than 10%, with a maximum error of 22% when estimates are compared to on-board measurements and less than 11% when estimates are compared to low-level estimates provided by the commercial tool.

Applications that operate on meshes are very popular in High Performance Computing (HPC) environments. In the past, many techniques have been developed in order to optimize the memory accesses for these datasets. Different loop transformations and domain decompositions are commonly used for structured meshes. However, unstructured grids are more challenging. The memory accesses, based on the mesh connectivity, do not map well to the usual linear memory model. This work presents a method to improve the memory performance which is suitable for HPC codes that operate on meshes. We develop a method to adjust the sequence in which the data are used inside the algorithm, by means of traversing and sorting the mesh. This sorted mesh can be transferred sequentially to the lower memory levels and allows for minimum data transfer requirements. The method also reduces the lower memory requirements dramatically: up to 63% of the L1 cache misses are removed in a traditional cache system. We have obtained speedups of up to 2.58 on memory operations as measured in a general-purpose CPU. An improvement is also observed with sequential access memories, where we have observed reductions of up to 99% in the required low-level memory size.

In this paper, the design tasks of wordlength optimization and architectural synthesis are combined. The benefits in comparison to the traditional sequential application of these two tasks are shown. A fine-grain combined wordlength optimization and architectural synthesis based on the use of simulated annealing is presented. As a result, a wider exploration of the design space is possible, thus reducing the implementation costs. The optimizer is tuned for DSP algorithms and is able to simultaneously optimize in terms of implementation area and output noise, thus leading to significant improvements. Moreover, heterogeneous-architecture FPGAs are addressed and the optimization is performed considering both look-up tables (LUTs) and embedded DSP resources. A complete comparison between the traditional sequential approach and the proposed combined approach is provided for FPGAs with and without DSP blocks. Area improvements of up to 21% are reported.

In this paper, a fixed-point quantization noise estimator aiming at Digital Signal Processing (DSP) algorithms is presented. The estimator enables significant reduction in the computation time required to perform complex word-length optimizations while providing a high accuracy. Affine Arithmetic (AA) is used to provide a Signal-to-Quantization Noise-Ratio (SQNR) estimation for differentiable non-linear algorithms with and without feedbacks. The estimation is based on the parameterization of the statistical properties of the noise at the output of fixed-point algorithms. This parameterization allows to relate the fixed-point formats of the signals with the output noise distribution by means of fast matrix operations. Thus, a fast estimation is achieved and the word-length optimization computation time is significantly reduced. The estimator is tested using a subset of non-linear algorithms such as vector operations, power computation IIR filter, adaptive filters, and channel equalizers. The Word-length optimization computation time is boosted by three orders of magnitude while keeping the average estimation error down to 6% for most cases.

The use of embedded multiplier blocks has become a norm in DSP applications due to their high performance and low power consumption. However, as their implementation details in commercial field-programmable gate arrays are not available to users, and the power estimates given by the tested low-level tool are not accurate enough to validate high-level models, the work on power estimation of these blocks is very limited. We present a dynamic power estimation methodology for the embedded multipliers in Xilinx Virtex-II Pro chips. The methodology is an adaptation of an existing power estimation method for lookup-table-based components and uses information about the type of architecture of the embedded block. The power model is characterized and verified by on-board measurements and is ready for integration with high-level power optimization techniques. The experimental results show that the average accuracy of the model is higher than the average accuracy of the low-level commercial tool.

Traditional approaches for fixed-point characterization are based on long simulations or additive noise models that do not show the nonlinear behavior of the quantization operations in reasonable time. In this paper, a novel interval-based approach that provides both tighter and faster results than the existing approaches is presented. It is based on a nonlinear adaptation of the quantization operations of affine arithmetic (AA). The results obtained with this method are compared to other published interval-based approaches, and the problem of interval oversizing is discussed in detail. Simulations show that: 1) the propagation techniques are not well suited to characterize the quantized linear systems with feedback loops; 2) the AA provides oversized bounds in this type of systems; and 3) the proposed adaptation does not provide guaranteed bounds as in the traditional interval-based computations, but it provides tighter estimates of the evolution in time of the ranges of the fixed-point signals and better runtime than the existing interval-based characterization techniques.

In this paper we address the high-level synthesis of multiple word-length DSP algorithms over programmable devices (FPGAs). Previous approaches tend to simplify the set of resources, thus alleviating the complexity of the high-level synthesis, but leading to non-optimal solutions. Here, we present a high-level synthesis framework that overcomes these limitations by means of considering: (i) both logic-based and embedded multipliers, (ii) both constant and generic multipliers and (iii) variable latency resources. A simulated annealing based approach for the combined scheduling, resource allocation and binding tasks is presented. When compared to previous approaches, area improvements of up to 60% are reported

Hardware implementation of arithmetic modules is a time-consuming task. Consequently, there is a demand for CAD tools that help the designer in reducing design times. This paper presents a floating-point module generator that allows user specification of the mantissa, exponent bit-width and clock period. This tool generates synthesizable VHDL code in a readable format that can be modified by the designer. It also optimizes circuit performance, providing modules with high-speed execution times, that are comparable to those of existing specific implementations.

This paper describes a novel technique, based on interval methods, for estimating reliability using fault trees. The approach encodes inherent uncertainty in the input data by modeling these data in terms of intervals. Appropriate interval arithmetic is then used to propagate the data through standard fault trees to generate output distributions which reflect the uncertainty in the input data. Through a canonical example of reliability estimation for a robot manipulator system, we show how the use of this novel interval method appreciably improves the accuracy of reliability estimates over existing approaches to the problem of uncertain input data. This method avoids the key problem of loss of uncertainty inherent in some approaches when applied to noncoherent systems. It is further shown that the method has advantages over approaches based on partial simulation of the input-data space because it can provide guaranteed bounds for the estimates in reasonable times.