This paper introduces the Pitanga platform and its potential as an alternative for FPGA remote laboratories. The platform consists of a virtual electronic board and a built-in virtual programmable logic device. The interface is innovative in that it utilizes a remote FPGA emulator running on standard x86 processors rather than a physical FPGA board. This software-based approach makes the platform more reliable, scalable, and accessible to low-budget institutions that may not have the resources to acquire traditional FPGA-based educational boards. Our live demonstration at ISCAS 2023 showcases the equivalence of experiments on the Pitanga platform and physical FPGA boards from a user's perspective, making it a viable option as a complement or alternative to traditional FPGA remote labs for digital circuit experimentation.

An incompletely specified Boolean function, also known as a Boolean relation, can be described by any combination of its on-set, off-set, and don't care (DC) set pairs. To transform a Boolean relation into a Boolean function (fully specified), we have to assign the DCs from the original specification. Depending on the DCs assignment, a better function minimization may result from the original specification. This article presents a method for joining two BDDs by describing the on-set and off-set of an incompletely specified$f$function into a single BDD for a fully specified coverage of the function. The proposed method is compared with the Restrict, Constrain and LICompaction methods implemented by the CUDD package, which are references for this problem using BDDs. In addition to these methods, we also compare our results with the Join method, which is a more recent proposal for the problem of assigning and minimizing incompletely specified Boolean functions. The LI-Compaction method presented the largest number of BDD nodes among the analyzed methods. Compared to the LICompaction method, the Restrict method produced 2.12% fewer nodes, the Constrain and Join methods produced 1.95% fewer nodes, while our method produced 24.80% fewer nodes.

In general, existing logic synthesis methods for majority logic are limited to 3-input gates (maj-3). However, since majority gates with larger fan-in have been proposed for different emerging nanotechnologies, it has become important to consider such gates in the synthesis process. This paper proposes a novel majority logic synthesis flow where the gates can have an arbitrary number of inputs. The proposed approach is based on the relationship between majority and threshold logic functions. The proposed methods obtain an average reduction of 10% on the number of nodes when compared to a previous work that uses both maj-3 and maj-5 gates. When compared to the previous maj-3 synthesis, the average reduction on number of nodes is 14%.

Combinational equivalence checking (CEC) has been widely applied to ensure design correctness after logic synthesis and technology-dependent optimization in digital integrated circuit design. CEC runtime is often critical for large designs, even when advanced techniques are employed. Three complementary ways for enabling parallelism in CEC are proposed, addressing different design and verification scenarios. The experimental results have demonstrated the speedups up to 63x when comparing the proposed approach to a single-threaded implementation of a similar CEC engine. A practical impact of such a speedup, for instance, is the runtime reduction from 19 h to only 18 min when checking equivalence of AND-inverter graphs comprising more than 20 million nodes. Therefore, the proposed solution presents great potential for improving current electronic design automation environments.

This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.

This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches.

This brief proposes the use of four-level forms in the memristive material implication (M-IMP) logic. M-IMP is a promising approach to perform stateful logic in memristive nonvolatile memories. In such a design technique, a given Boolean function is evaluated as a sequence of instructions, making logic synthesis methods necessary to attain the shortest sequence. In comparison to previous work, experimental results have shown an average reduction of 40% when evaluating the tradeoff between the numbers of instructions and memristive devices.

Parallel computing is a trend to enhance scalability of electronic design automation (EDA) tools using widely available multicore platforms. In order to benefit from parallelism, well-known EDA algorithms have to be reformulated and optimized for multicore implementation. This paper introduces a set of principles to enable a fine-grain parallel AND-inverter graph (AIG) rewriting. It presents a novel method to discover and rewrite in parallel parts of the AIG, without the need for graph partitioning. Experiments show that, when synthesizing large designs composed of millions of AIG nodes, the parallel rewriting on 40 physical cores is up to 36x and 68x faster than ABC commands rewrite −l and drw, respectively, with comparable quality of results in terms of AIG size and depth.

This paper presents two main contributions toward efficient VLSI circuits mapped with simple cells: (1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and (2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. We show that efficient implementations in terms of inverter count, transistor count, area, power and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while (i) optimizing the number of added inverters; and (ii) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.

This paper discusses directions for a VLSI design flow based on a novel paradigm of local logic computation and global signal distribution. In the last years there has been an increasing effort to perform a better integration between logic synthesis and physical design, with the aim to bring technology information into early design steps. The proposed paradigm shift can be very helpful to attain this integration.

In this paper, a straightforward and effective method to identify threshold logic function (TLF) is presented. Threshold logic is a promising alternative to conventional Boolean logic due to its suitability for emerging technologies, like memristors, quantum-dot cellular automata, resonant tunneling device, and spintronic devices. Identification and synthesis of TLF are essential tasks in a design flow based on such a logic strategy. The proposed method relies on irredundant sum-of-products Boolean function description form and exploits both ordering of variables and system of inequalities to assign the variable weights and the function threshold value. This is the first heuristic algorithm able to identify all threshold functions with up to six variables, being also more effective than other heuristic methods for functions with a larger number of variables. For functions obtained from k -cuts of benchmark circuits, experimental results demonstrated effectiveness near to 100% when compared to exact methods, even when the number of function variables increases. The execution time of the proposed approach is similar to related heuristic methods, being faster than integer linear programming-based algorithms.

The fast-extract algorithm is a well-known algebraic method for factoring and decomposing Boolean expressions. Since it uses pairwise comparisons between cubes to find factors, the runtime is degraded for networks whose primary outputs are expressed in terms of primary inputs and have Boolean functions with thousands of cubes. This paper describes a new implementation of the fast-extract algorithm, fxch, having complexity linear in the number of cubes. The reduction in complexity is achieved by hashing sub-cubes and using the hash table to find good factors to extract. Experimental results on industrial benchmarks show superior runtime and scalability of the proposed algorithm, compared to the available solutions.

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods.

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

Transistor scaling is the major contributor toward continuous improvement of circuit performance. However, the reduction of transistor dimensions increases several fabrication and design challenges. In this sense, several post CMOS devices are being investigated. Recently, the magnetoresistive spin-diode was proposed and the possibility to implement logic gates exploiting this kind of device has been demonstrated. The spin-diode technology has the INV, NOR2 and XNOR2 as basis logic functions, which is quite different from the CMOS basic gates. This paper proposes an algorithm that improves the state-of-the-art synthesis algorithm for the spin-diode technology. Also, this paper presents some optimized designs of functions that appear frequently in circuits. Results show a reduction of more than 3% in number of diodes, compared to the state-of-the-art algorithm.

This paper presents a novel approach to synthesize circuits based on threshold logic gates (TLGs). Emerging technologies, such as memristors, spintronics devices and tunneling diodes, are able to build this class of gates efficiently. For this reason, threshold logic is a promising alternative to conventional CMOS logic. The proposed approach is based on pruning non-threshold-logic cuts in order to limit the search space during technology mapping. As a result, both the number of TLGs and logic depth of the synthesized circuits are reduced. Experimental results have shown that, compared to the state-of-the-art methods, the TLG count is reduced by 8% and logic depth is reduced by 46%.

This paper presents a new approach for Boolean decomposition based on the Boolean difference and cofactor analysis. Two simple tests provide sufficient and necessary conditions to identify AND and exclusive-OR (XOR) decompositions. The proposed method can decompose an n-input function in O(n • log n) cofactor and O(n) equivalence test operations. Recently, 2-to-1 multiplexers (MUX) have also been used to perform such decomposition. However, MUX with more inputs has been neglected. We provide sufficient and necessary conditions to obtain MUX decompositions of functions with an arbitrary number of inputs.

This work presents an efficient algorithm to obtain a material implication (IMPLY) expression from a sum-of-products (SOP). The resulting expression is computable with two work memristors. The proposed method has linear time complexity with respect to the SOP size. Comparison to previous work shows a reduction on the average number of IMPLY operations when applying the proposed method.

This paper presents two contributions to logic synthesis for memristive stateful logic. Firstly, we demonstrate the necessity to correct results provided by existing logic synthesis methods to ensure the expected computation. Secondly, we propose the concept of multi-memristor implication as a generalization of multi-input implication. Experimental results have shown a reduction of 6.5% in the number of operations when compared to previous works.

This paper presents a novel analytical delay model to perform fast estimation of signal delay propagation over buffer chain under time-dependent dielectric breakdown (TDDB) aging effect. The proposed model considers all gate-to-drain, gate-to-source and gate-to-bulk breakdowns effects, and relies on accurate modeling of TDDB. In comparison to SPICE simulation, based on BSIM4 transistor model, experimental results have shown an average error of 1.65%, whereas 98% of the cases present an estimation error of at most 5%.

This paper presents the 15nm FinFET-based Open Cell Library (OCL) and describes the challenges in the methodology while designing a standard cell library for such advanced technology node. The 15nm OCL is based on a generic predictive state-of-the-art technology node. The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms. Developing a 15nm standard cell library brings out design challenges which are not present in previous technology nodes. Some of these challenges include double-patterning for both metal and poly layers, a very restrictive set of physical design rules, and the demand for lithography-friendly patterns. This paper discusses the development of the library considering the challenges associated with advanced technology nodes.

This paper presents an improved benchmark suite to jointly consider logic synthesis and physical design. Usually, benchmark circuits were provided by the physical design and the logic synthesis communities separately, according to their specific needs. The files provided for each benchmark set were restricted to the views necessary for the community. Additional specifications of design intents are necessary to express optimization goals that can be shared by logic synthesis and physical design communities, as circuits alone do not carry sufficient information to establish a benchmark with a clear optimization goal. In this paper, we describe benchmarks as a set composed of circuits, design intents (constraints), floorplan, target library and technology. Disregarding pieces of information provided for the benchmarks can change the associated criticality and affect the combined or isolated outcome of logic synthesis and physical design. The proposition of this benchmark suite brings attention to the problem of considering adequately the complete context of design intent throughout the flow.

This paper presents an accurate analytical delay model for CMOS inverter considering both subthreshold and superthreshold operating regions. Previous related work are either only valid for a specific operating condition or assume a step input. Therefore, that is the first approach to consider both different operating regions and input transition time. Moreover, the proposed model also considers several second order effects that influence the CMOS inverter dynamic behavior. Compared to electrical simulations based on BSIM4 transistor model the proposed delay model presents an average error of 2.3% and the worst case error of 6.6%.

In this paper, a novel method to synthesize circuits based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS integrated circuits due to its suitability to emerging technologies, such as tunneling diodes, memristors and spintronics devices. A constructive process is applied to generate optimized TLG networks taking into account multiple goals and design costs, including gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits have shown an average gate count reduction of circa 32%, reaching up to 54% in some cases, in comparison to related approaches.

The transistor arrangement optimization is an effective possibility to improve VLSI design, especially when generating CMOS logic gates to be inserted in standard cell libraries. This paper addresses this issue and presents a new methodology to generate efficient transistor networks. Starting from an input ISOP, the proposed method is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. By applying the proposed approach, it is possible to achieve optimized transistor arrangements since greedy choices are avoided during part of the generation process. The performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.

Every Boolean function has a unique property called Minimum Decision Chain (MDC). This paper proposes an effective way to compute this property for arbitrary functions. The proposed method is very efficient when compared to a more direct and intuitive approach, that is used as the reference for performance analysis. Different examples have been evaluated, and the results are discussed. The proposed method is able to compute the MDC value in order of milliseconds, allowing the use of MDC computation to guide logic synthesis algorithms.

Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.

This work proposes design strategies applicable to self-test circuits for the functional validation of latches and flip-flops. The proposed methodology is also useful for, delay test and power consumption analysis that can also be performed over the circuits under test. Moreover, the evaluation of the impacts on circuit operation due to power supply variations and nanometer aging effects can be explored through the self-timed execution mode by monitoring the run frequency. The self-timed and self-checking characteristics make the proposed solutions very attractive for testing standard cell libraries as well as for comparing different implementations of such storage elements. We have validated the addressed strategies at transistor level through electrical simulations.

This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the concept of factor cuts is extended to kl-cuts. Algorithms for computing this kind of cuts, including kl-cuts with unbounded k, are presented and results are shown. As a practical application, a covering algorithm using these cuts is presented.

This paper introduces a new algorithm for Boolean factoring. The proposed approach is based on a novel synthesis paradigm, functional composition, which performs synthesis by associating simpler sub-solutions with minimum costs. The method constructively controls characteristics of final and intermediate functions, allowing the adoption of secondary criteria other than the number of literals for optimization. This multi-objective factoring algorithm presents interesting features and advantages when compared to previous works.

This work proposes a simple, efficient and easy-to-use test circuit for evaluating and validating any set of logic gates in terms of functionality, performance, power consumption and impact in operation of sub-nanometer physical effects.

This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with multi-level series-parallel devices. Experimental results have been carried out on different fabrications processes, and good correlation with HSPICE simulator was obtained at cell and circuit levels. The algorithm presents a speed up of 80x when compared to HSPICE.

This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results.

This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.

This paper proposes a protocol for data exchange to allow the communication of specialized tools with Eletronic Design Automation (EDA) frameworks. The BICO (BasIc type COnversor) protocol is based on SOAP, a Web-Service technology. The aim of BICO is to support interoperability, integration and cooperation between scripting and general-purpose languages, with minimum programming effort. The BICO protocol is able to automatically encode and decode data structures used as parameters of requests and replies of services implemented in different languages. Beyond the coder and decoder (CODEC) itself, a helper tool for the creation of the definitions needed by the protocol and some basic communication mechanisms is provided. Case studies are used to demonstrate the integration of specialized tools with commercial frameworks. The proposed protocol achieves interoperability with a simple and easy-to-learn mechanism and yet is very efficient for the purposes it was designed. The proposed integration method has learning costs affordable by university and small developers that want their tools linked to commercial environments or frameworks.

This paper addresses the question of how many serial switches are necessary to implement a given logic function as a switch network. This issue is important because it affects directly the resistance that will be charging/discharging output loads, thus affecting cell and circuit performance. We derive exact lower bounds to easily evaluate the number of serial switches needed and demonstrate that complementary series/parallel (CSP) and pass transistor logic (PTL) topologies exceed the lower bounds for many practical examples. We also propose a design methodology that produces cells with minimum number of transistors in series and evaluate the benefits obtained in circuit delay.