Attribute-based encryption (ABE) requires several elliptic-curve-based functions, including elliptic-curve scalar multiplication (ECSM), hashing to the curve, and pairing. Although these computations share underlying similarities, prior hardware designs have shown that distinct architectures yield better performance for each function. Consequently, it remains unclear which architecture offers optimal performance when supporting all required functions within a unified design. In this work, we present a design space exploration methodology in which the design is parameterized using a defined set of design parameters, and an automatic schedule generator is employed to estimate the cycle counts for each function. This allows us to identify the configuration that minimizes latency for both individual functions and complete cryptographic operations. The versatility of our approach is demonstrated through two case studies: 1) ECSM over Curve25519, Secp256k1, NIST-P256, and NIST-P384; and 2) multiple elliptic-curve functions over the BLS12-381 curve. In the first case, the optimal configuration implemented on a Virtex7 field-programmable gate array (FPGA) achieves up to a 15% latency reduction compared to state-of-the-art designs. In the second case, the unified accelerator in its optimal configuration supports all core ABE functions and achieves superior latency or throughput-per-area (TPA), and in some cases both, compared to existing designs.

Homomorphic encryption (HE), including Cheon– Kim–Kim–Song (CKKS), enables secure cloud computation over encrypted data. While prior work predominantly accelerates cloud-side evaluation, the client-side remains a critical and underexplored bottleneck. This article presents a dedicated hardware accelerator for client-side CKKS preparation. Specifically, we make three key contributions: a unified multiplier architecture that supports both number theoretic transform (NTT) and fast Fourier transform (FFT) to avoid logic duplication and reduce area; an in-place memory organization with relaxed layout constraints to improve data reuse and lower on-chip storage overhead; and a dynamic twiddle factor (TF) generator that removes large prestored constant tables while preserving low-latency. The proposed design efficiently implements CKKS encoding, encryption, decryption, and decoding, enabling low-latency secure interactions. Evaluation on TSMC 28-nm ASIC and Xilinx UltraScale+ FPGA shows over 40% reduction in area/gate count compared with representative hardware baselines and a$1.2\times $end-to-end speedup for client-side CKKS operations, demonstrating the design’s practicality for efficient homomorphic data preparation.

Modular multiplication is a fundamental operation in many cryptographic systems, with its efficiency playing a crucial role in the overall performance of these systems. Since many cryptographic systems operate with a fixed modulus, we propose an enhancement to the fixed modulus lookup table (LuT) method used for modular reduction, which we refer to as the manipulated LuT (MLuT) method. Our approach applies to any modulus and has demonstrated comparable performance compared with some specialized reduction algorithms designed for specific moduli. The strength of our proposed method in terms of circuit performance is shown by implementing it on Virtex7 and Virtex Ultrascale+ FPGA as the LUT-based MLuT modular multiplier (LUT-MLuTMM) with generalized parallel counters (GPCs) used in the summation step. In one-stage implementations, our proposed method achieves up to a 90% reduction in area and a 50% reduction in latency compared with the generic LuT method. In multistage implementations, our approach offers the best area-interleaved time product, with improvements of 39%, 13%, and 29% over the current state-of-the-art for ~256-bit, SIKE434, and BLS12-381 modular multipliers, respectively. These results demonstrate the potential of our method for high-performance cryptographic accelerators employing a fixed modulus.

This study presents a logic-locking scheme based on the binary ring learning with error (bin-RLWE) algorithm, implemented in a reduced instruction set computer-five (RISC-V) system-on-chip (SoC) design. Unlike traditional logic-locking methods that require providing users with raw locking parameters, the proposed approach secures critical logic paths in the privilege switching process without exposing these sensitive parameters. The implemented locking module itself consumes 3519 lookup tables (LUTs) and 2645 registers, leading to an overall overhead of 6.0% in LUTs and 6.9% in registers compared to the baseline system. The unlock process requires about$2.6~\mu $s, introducing moderate performance impact and primarily affecting system-level operations while preserving user-level computational efficiency.

The deep learning technique has been applied in a wide range of applications. The development of cloud computing further expands the application scenarios of deep learning but brings privacy issue. Homomorphic Encryption (HE), as a cryptographic solution, has attracted much attention in recent years. While some research applies HE on forward neural networks (FNNs), the research on recurrent neural networks (RNN) is still rare because the deep recurrent operation is hard to implement with HE. In this paper, we propose the first gated recurrent unit (GRU) network on HE scheme without bootstrapping, which is very expensive that takes 73% calculation time in the former encrypted GRU design. We introduce several techniques to reduce the multiplicative depth to 8 per recurrent step and allow 7 recurrent steps in our model. Processing long input sequences is also available by a rearranging method to control the recurrent steps less than 7. The testing results show that there is nearly no accuracy degradation between our encrypted GRU and the original unencrypted model. Also, we highly improve the throughput by a packing strategy. On MNIST dataset, we achieve 98.6% accuracy, which is totally the same as the unencrypted result. The throughput is 439 images/hour, which is 360 times higher than the former design. Furthermore, we test more complex natural language processing (NLP) task, which is a dominant application of RNNs. Our encrypted GRU network achieves 90.0% accuracy on AG-news dataset, almost the same as the unencrypted GRU model of 90.3%. The results indicate that the encrypted GRU design can provide accurate, efficient and privacy-preserving predictions.

With the rise of the fabless business model, security threats, including Intellectual Property (IP) theft, overproduction, counterfeiting, and reverse engineering, have increased. This paper introduces Dynamic Digital Circuit Locking (DDCL) as a method to counteract these threats. At its core, DDCL utilizes dynamic logic gates for locking. These gates mimic the operation of standard logic gates through a dynamic process, thereby exploiting adversaries who depend on static digital circuit analysis. As a result, DDCL can resist all static analysis attacks more effectively than conventional techniques. DDCL surpasses earlier methods by its reliance on logic loops for proper operation, which makes loop breaking attacks less effective. However, the advanced security offered by DDCL also presents challenges, such as increased power consumption and circuit complexity. This paper further examines the structure, security aspects, and comparative performance of DDCL. It underscores its value in multi-vendor scenarios and its compatibility with existing IP cores, which require only minor changes to original designs, thereby illustrating the practical role of DDCL in enhancing hardware security.

We have designed and fabricated a multi-core, multi-pairing crypto-processor on BN curve over 254bit prime field in 65nm CMOS process. We have designed optimal 2- layer sequencer for flexible operation, realizes up to 96.7% computation efficiency, with canceling data I/O overhead by double buffer architecture. Measurement results demonstrate 3.0 times faster with optimal 12-thread scheduling, and 2.9 times higher throughput and 1.7 times smaller energy consumption with 3-parallel scheduling than ever reorted. Flexible architecture enables to be utilized and accelarate the advanced crypto- algorithm such like inner product encryption and searchable encryption.

We propose a polynomial multiplier for lattice-based cryptography that achieves a throughput of 24.2 times higher than the state-of-the-art design. We have optimized the proposed architecture for ASIC implementation, instead of FPGA or CPU implementation. We employed shift register to reorder values to avoid complex memory accesses, and we realize complete pipeline operation for higher throughput. Also, we show that raising the degree of parallelism in this design increases throughput per area. This work will lead to the acceleration of Ring-LWE and Module-LWE-based cryptography, which attracts much attention for its resistance to quantum computers and applications in fully homomorphic encryption (FHE).

To improve throughput of Electron Beam Direct Writing (EBDW) with Character Projection (CP) method, we propose a structured routing architecture (SRA) where VIA placement and wire-track interchange is restricted so as to reduce possible layout patterns in VIA and metal layers. CP exposure is accelerated by the increased figure numbers of VIAs and metal segments in each CP character due to the reduced character variations. We demonstrate a design flow that enables routing on the interconnect layer with the limited flexibility using a commercial routing tool and a few own programs. We also present a methodology to design character stencils with improved area efficiency by character superposition. Our experimental results proved the architecture's feasibility in achieving the target EBDW performance in 14nm technologies.