Mathematical morphology is a promising computer paradigm based on set theory and has many applications in image processing. Although some architectures have been proposed, there are as yet no compact, practical computers that can handle a variety of morphological operations with large, complex structuring elements at video rates. This has prevented the great potential of morphology from being fully realized. This paper describes a morphology processing method that uses a highly parallel two-dimensional (2-D) cellular automaton architecture called it CAM2 (Cellular AutoMata on Content Addressable Memory). New mapping methods achieve high-throughput complex morphology processing. Evaluation results show that CAM2 performs one morphological operation for basic structuring elements within 30 micros. Furthermore, CAM2 can also handle an extremely large and complex structuring element of 100x100 at video rates. CAM2 will increase the potential use of morphology and make a significant contribution to the development of various real-time image processing systems.

In this correspondence, a parallel algorithm, in order to extract parametric curves from a two-dimensional (2-D) image space, is proposed. It is based on the Hough transform (HT) and uses the content addressable memory (CAM) as the main processor. A set of simulated results for circular shape extraction are presented in order to demonstrate its merit. Hence, voting, thresholding, and three-dimensional (3-D) peak extraction are efficiently performed within the CAM. In addition, and in order to reduce the quantization errors, a weighted AT algorithm (WHT), which uses a weighted voting is proposed. Experimental results indicate that a real-time shape extraction for an image 256/spl times/256 can be achieved within a small amount of hardware. Therefore, CAM-based HT can be considered as a promising attraction for next generation pattern recognition platforms.

This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in a 0.25 /spl mu/m four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability, The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final embedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software.

Cellular automaton (CA) is a promising computer paradigm that can break through the von Neumann bottleneck. Two-dimensional CA is especially suitable for application to pixel-level image processing. Although various architectures have been proposed for processing two-dimensional CA, there are no compact, practical computers. So, in spite of its great potential, CA is not widely used: This paper proposes a highly-parallel two-dimensional cellular automaton architecture called CAM/sup 2/ and presents some evaluation results. CAM/sup 2/ can attain pixel-order parallelism on a single board because it is composed of a CAM, which makes it possible to embed an enormous number processing elements (PEs), corresponding to CA cells, onto one VLSI chip. Multiple-zigzag mapping and dedicated CAM functions enable high-performance CA processing. The performance evaluation results show that 256 k CA cells, which correspond to a 512/spl times/512 picture, can be processed by a CAM/sup 2/ on a single board using deep submicron process technology. The processing speed is more than 10 billion CA cell updates per second. This means that more than a thousand CA-based image processing operations can be done on a 512/spl times/512 pixel image at video rates (33 msec). CAM/sup 2/ will widen the potentiality of CA and make a significant contribution to the development of compact and high-performance systems.

This paper proposes a real-time morphology processing method based on a highly-parallel 2D cellular automata called CAM/sup 2/ (cellular automata on content addressable memory) that can attain pixel-order parallelism (several hundred thousands) on a single PC board. Evaluation results show that CAM/sup 2/ can perform various types of morphology processing within video rates, indicating it could be a promising platform for processing morphology.

We describe real-time straight line extraction system and evaluate it. The main part of our system involves a highly parallel processing board on which a highly parallel Hough transform algorithm is mounted. We used the Hough transform, because it useful in line detection. In this board, a content addressable memory (CAM) LSI with dedicated functions for highly parallel image processing is used in this board. Both voting and peak extraction, which make up the Hough transform, are directly executed by the CAM. The CAM acts as a PE (processing element) array that performs highly parallel processing for the Hough transform and it also acts as a memory for two-dimensional Hough space. Sixteen thousand Hough points can be mapped at once and thousands more can be mapped by time-sharing in one CAM. Also variable Hough point resolution is available, because the CAM-based HT algorithm on this board is scalable. Thus line extraction by the Hough transform of 16-K point Hough space for a 256/spl times/256 picture can be carried out at video-rates by using a Hough board with a single CAM chip. Moreover a Hough transform with weighted voting for noisy images can also be achieved at video-rates.

This paper proposes a real-time content addressable memory (CAM)-based Hough transform algorithm for straight line detection and evaluates its performance. Both voting and peak extraction, which compose the Hough transform, are directly executed by CAM. The CAM acts as a processing element (PE) array that performs highly parallel processing for the Hough transform and also as a memory for two-dimensional Hough space. To achieve high-speed processing, voting is executed in every scanning line, not every pixel. The Hough space is mapped into the CAM in folded form to reduce the size of the CAM hardware. Moreover, CAM-based weighted voting achieves more accurate line detection in spite of the quantization error and noise in the image space. Simulations of CAM hardware size, processing time and the accuracy of line detection show that a real-time and high-resolution Hough transform for a 256/spl times/256 picture can be achieved using a single CAM chip with current VLSI technology. This CAM-based Hough transform algorithm promises to be an important step towards the realization of a real-time and compact image understanding system.

An architecture and its four load balancing algorithms for a highly OR-parallel inference machine are proposed, and its performance is evaluated in a trace-driven simulation study. This inference machine consists of a large number of processing elements (PEs) with serial I/O links directly connected to each other in a simply modified mesh network. Each PE is a high-speed sequential Prolog processor with its own local memory. The activity of all PEs is locally controlled by four new load balancing algorithms based on purely local communication. Communication is allowed only between directly connected PEs. These load balancing algorithms reduce communication overhead in a load balancing and make it possible to accomplish highly OR-parallel execution. A software simulator using a trace-driven simulation technique based on an inference tree has been developed, and some typical OR-parallel benchmarks such as the n-queens problem have been simulated on it. The average communication per load balancing is reduced by a factor ranging from 1/30 to 1/100 by the interaction of these load balancing algorithms as compared with a conventional copying method. The inference machine (1024 PEs; 32/spl times/32 array) attains 300-600 times parallel speedup, assuming 1 MLIPS (mega logical inferences per second) PE and a 20 MBPS (mega bits per second) each serial I/O link, which could be easily integrated on a single chip using current VLSI technology. This highly OR-parallel inference machine promises to be an important step towards the realization of a high-performance artificial intelligence system.>

This paper proposes a new moving-objects tracking method processed by a local spiral labeling with CAM (Content Addressable Memory). The local spiral labeling method was proposed in order to improve one of the shortcomings of TV telephones. The conventional labeling, however, needs huge processing time and a memory capacity in order to compute connecting relations between label numbers. CAM has some functions to search and write the plural contents of the memory at the same time. CAM is suitable for a real time labeling. This paper shows a new labeling algorithm called local spiral labeling, a real-time labeling scheme utilizing CAM, and a prototype system of human head tracking using 0.5 micrometers BiCMOS gate-array technology.

A content addressable memory (CAM)-based machine architecture is proposed for a high-speed Prolog machine. This Prolog machine attempts to speed up the total Prolog execution performance by using a hierarchical pipelined scheme and a CAM-based backtracking scheme. The hierarchical pipelined scheme reduces the total number of Prolog execution steps to half of that using the conventional method. The CAM-based backtracking is efficiently and quickly achieved by using CAM's sophisticated garbage collection function, which eliminates the need for stacks and additional operation cycles. In this machine, all Prolog execution can be simply controlled by a semantic information 'inference depth' without any address handling by storing all working information, binding and control information, in CAMs. This machine attains a performance of 100 KLIPS (kilo logical inference per second) on the deterministic append program in the interpretive mode, and also attains high performance in the nondeterministic program.>