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Hideyuki Kikuchihara

dblp:29/2146 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 80% Hardware reliability and fault tolerance · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › timing analysis
dynamic timing analysis		 0.011985
ACTAS: an accurate timing analysis system for VLSI · DAC 1985
Electronic design automation › timing analysis
static timing analysis		 0.011985
ACTAS: an accurate timing analysis system for VLSI · DAC 1985
Electronic design automation
timing analysis		 0.011985
ACTAS: an accurate timing analysis system for VLSI · DAC 1985
Hardware reliability and fault tolerance › error detection
timing error detection		 0.011985
ACTAS: an accurate timing analysis system for VLSI · DAC 1985
Electronic design automation › hardware verification and test
timing verification		 0.011985
ACTAS: an accurate timing analysis system for VLSI · DAC 1985

Methods — techniques the papers use, named apart from their topics

path delay calculation · 0.0behavior analysis · 0.0
YearPublicationVenuePosition
1985 ACTAS: an accurate timing analysis system for VLSI
abstract
This paper describes a timing analysis system (ACTAS: ACcurate Timing Analysis System). This system analyzes the logical behaviors of VLSI. It verifies timings at flip-flops and detects timing errors. Then, it calculates path delays of the partial combinational circuits generating the errors. If they do not satisfy timing constraints, the system detects error paths. In this system, the former method based on behavior analysis is called DYNAMIC TIMING ANALYSIS and the latter method based on path analysis is called STATIC TIMING ANALYSIS. By use of this system, it improves the timing analysis efficiency of the complicated timing of VLSI.
Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa
 DAC3