Abstract Effective water management in underground mining requires maintaining safe reservoir levels while minimizing the high energy costs of continuous pumping. Although flexible electricity pricing enables cost-aware operation, traditional threshold-based controllers cannot exploit this flexibility efficiently. This paper presents an industrial case study on efficient mine dewatering using reinforcement-learning-based control synthesized with the Uppaal Stratego framework. A baseline threshold controller is first implemented, followed by a reinforcement-learning controller trained on forecast inflows and day-ahead electricity prices to minimize pumping costs while limiting pump switching. To ensure safety during learning without distorting the optimization objective, we introduce a pre-shield that blocks unsafe transitions. We formally show that this pre-shield is maximally permissive with respect to a monotonicity safety objective. Simulation results demonstrate that the learning-based strategy reduces total energy consumption by up to 40% compared to threshold-based control, while maintaining safe operation in all scenarios.

To address safety concerns in industrial systems, we propose a framework for forecasting CPU load with respect to a predetermined threshold, allowing customers to add tasks from a predefined library. Existing tools, akin to Windows Task Manager, provide limited insights due to their aggregate nature and high computational overhead. Our approach uses conformal prediction for rapid uncertainty-aware forecasts and Shapley value analysis to quantify individual task contributions to the CPU load. This proof-of-concept framework improves system safety assessment by addressing key research questions in load prediction and validation, paving the way for refined measurement methodologies in industrial applications.

Abstract Integrating machine learning into computer architecture simulation offers a new approach to performance analysis, moving away from traditional algorithmic methods. While existing simulators accurately replicate hardware, they often suffer from slow execution, complex documentation, and require deep CPU knowledge, limiting their usability for quick insights. This paper presents a deep learning-based approach for simulating a key CPU component, cache memory. Our model “learns” cache characteristics by observing cache miss distributions, without needing detailed manual modeling. This method accelerates simulations and adapts to different program needs, demonstrating accuracy comparable to traditional simulators. Tested on Sysbench and image processing algorithms, it shows promise for faster, scalable, and hardware-independent simulations.

Digital Twins (DTs) are virtual representations of physical products in many dimensions, such as geometry and behaviour. As a backbone of Industry 4.0, DTs help interpret and even predict the behaviour of physical processes, provide a virtual testbed for maintenance and upgrade, and enable automatic decision-making supported by artificial intelligence. Despite the promising future, challenges exist, such as the absence of a framework that facilitates the development and application of DTs in industrial contexts. We propose a service-oriented architecture (SOA) DT framework for dynamic and robust distributed systems. The framework contains two types of services. One includes the services provided to the users and is supported by an orchestration mechanism to ensure a quality of service (QoS). The other one refers to the common functions of all DTs. Further, we describe the DT-based decision-making enabled by our QoS-oriented learning of the framework and a Hoare-logic-based verification of QoS.

Digital Twins (DTs) serve as the backbone of Industry 4.0, offering virtual representations of actual systems, enabling accurate simulations, analysis, and control. These representations help predict system behaviour, facilitate multiple real-time tests, and reduce risks and costs while identifying optimization areas. DTs meld cyber and physical realms, accelerating the design and modelling of sustainable innovations. Despite their potential, the complexity of DTs presents challenges in their industrial application. We continue here the development of our approach to build an adaptable and trustable framework for building and operating DT systems - A Digital Twin Framework for Dynamic and Robust Distributed Systems (D-RODS). D-RODS aims to address the challenges above, aiming to advance industrial digitalization and targeting areas like system efficiency, incorporating AI and verification techniques with formal support. We employ existing large-usage tools to illustrate the approach in development based on a synthetic adaptable use case.

Many hardware solutions for Power over Ethernet (PoE) Power Sourcing Equipment (PSE) exist, with slightly varying feature sets. A software solution is needed for interaction with the PSEs, and for managing a power budget across several PSEs. A generic interface is desirable, as well as generic software components that can be used in support of several PSE solutions. In this paper we present a union of features and real-time requirements for three hardware solutions, and the development of a generic software architecture.

We present LLM-shark, a tool for automatic hardware resource-boundness detection and cache-partitioning. Our tool has three primary objectives: First, it determines the hardware resource-boundness of a given application. Secondly, it estimates the initial cache partition size to ensure that the application performance is conserved and not affected by other processes competing for cache utilization. Thirdly, it continuously monitors that the application performance is maintained over time and, if necessary, change the cache partition size. We demonstrate LLM-shark’s functionality through a series of tests using six different applications, including a set of feature detection algorithms and two synthetic applications. Our tests reveal that it is possible to determine an application’s resource-boundness using a Pearson-correlation scheme implemented in LLM-shark. We propose a scheme to size cache partitions based on the correlation coefficient applications depending on their resource boundness.

In this paper, we describe the creation of resource usage forecasts for applications with unknown execution characteristics, by evaluating different regression processes, including autoregressive, multivariate adaptive regression splines, exponential smoothing, etc. We utilize Performance Monitor Units (PMU) and generate hardware resource usage models for the L2-cache and the L3-cache using nine different regression processes. The measurement strategy and regression process methodology are general and applicable to any given hardware resource when performance counters are available. We use three benchmark applications: the SIFT feature detection algorithm, a standard matrix multiplication, and a version of Bubblesort. Our evaluation shows that Multi Adaptive Regressive Spline (MARS) models generate the best resource usage forecasts among the considered models, followed by Single Exponential Splines (SES) and Triple Exponential Splines (TES).

The paper introduces elements of a service based perspective of a scalable and dynamic automation system architecture. The approach is based on potentially multi-role devices (implementing node management, processing and networking functionalities) hosting a set of services requested by input nodes. In addition, artificial intelligence support is described to provide means of reaching deployment optimality and reliability. Formal approaches are deemed necessary for both verification of the artificial intelligence approach and of the resulting solutions. A model-based design path is complementary considered in order to lead to an increased efficiency in resource utilization, to lowering design efforts, and ensure a formally correct allocation of services, according to system requirements and constraints.

In this paper, we present a last-level cache partitioning controller for multi-core systems. Our objective is to control the Quality of Service (QoS) of applications in multi-core systems by monitoring run-time performance and continuously re-sizing cache partition sizes according to the applications' needs. We discuss two different use-cases; one that promotes application fairness and another one that prioritizes applications according to the system engineers' desired execution behavior. We display the performance drawbacks of maintaining a fair schedule for all system tasks and its performance implications for system applications. We, therefore, implement a second control algorithm that enforces cache partition assignments according to user-defined priorities rather than system fairness. Our experiments reveal that it is possible, with non-instrusive (0.3-0.7% CPU utilization) cache controlling measures, to increase performance according to setpoints and maintain the QoS for specific applications in an over-saturated system.

In this paper, we evaluate different methods for statistical determination of application resource dependency in multi-core systems. We measure the performance counters of an application during run-time and create a system resource usage profile. We then use the resource profile to evaluate the application dependency on the specific resource. We discuss and evaluate two methods to process the data, including moving average filter and partitioning the data into smaller segments in order to interpret data for correlation calculations. Our aim with this study is to evaluate and create a generalizeable methods for automatic determination of resource dependencies. The final outcome of the methods used in this study is the answer to the question: "To what resources is this application dependent on?". The recommendation of this tool will be used in conjunction with our last-level cache partitioning controller (LLC-PC), to make decision if an application should receive last-level cache partition slices.

In this paper we present a methodology to be used for quantifying the level of performance isolation for a multi-core system. We have devised a test that can be applied to breaches of isolation in different computing resources that may be shared between different cores. We use this test to determine the level of isolation gained by using the Jailhouse hypervisor compared to a regular Linux system in terms of CPU isolation, cache isolation and memory bus isolation. Our measurements show that the Jailhouse hypervisor provides performance isolation of local computing resources such as CPU. We have also evaluated if any isolation could be gained for shared computing resources such as the system wide cache and the memory bus controller. Our tests show no measurable difference in partitioning between a regular Linux system and a Jailhouse partitioned system for shared resources. Using the Jailhouse hypervisor provides only a small noticeable overhead when executing multiple shared-resource intensive tasks on multiple cores, which implies that running Jailhouse in a memory saturated system will not be harmful. However, contention still exist in the memory bus and in the system-wide cache.

In this paper we present an embedded systems design flow, supporting variations in technology - hardware vs. software - at implementation time. The work builds on seasoned and new approaches, tools and techniques, such as software production lines, FPGA design, and high level synthesis. We define the necessary context for such a design flow to succeed, and introduce supporting tools and interfaces to enable the designer to take decisions, which are further automatically transferred into the synthesis phases. We exemplify our solutions on a motor controller design, considering several features that are potentially required to be implemented, and where all the elements are possible to be implemented either as hardware or software modules.

The current trend in automotive systems is to integrate more software applications into fewer ECU's to decrease the cost and increase efficiency. This means more applications share the same resources which in turn can cause congestion on resources such as such as caches. Shared resource congestion may cause problems for time critical applications due to unpredictable interference among applications. It is possible to reduce the effects of shared resource congestion using cache partitioning techniques, which assign dedicated cache lines to different applications. We propose a cache partition controller called LLC-PC that uses the Palloc page coloring framework to decrease the cache partition sizes for applications during runtime. LLC-PC creates cache partitioning directives for the Palloc tool by evaluating the performance gained from increasing the cache partition size. We have evaluated LLC-PC using 3 different applications, including the SIFT image processing algorithm which is commonly used for feature detection in vision systems. We show that LLC-PC is able to decrease the amount of cache size allocated to applications while maintaining their performance allowing more cache space to be allocated for other applications.

We investigate the effects on the execution time, shared cache usage and speed-up gains when using datapartitioned parallelism for the feature detection algorithms available in the OpenCV library. We use a data set of three different images which are scaled to six different sizes to exercise the different cache memories of our test architectures. Our measurements reveal that the algorithms using the default settings of OpenCV behave very differently when using data-partitioned parallelism. Our investigation shows that the executions of the algorithms SURF, Dense and MSER correlate to L3-cache usage and they are therefore not suitable for data-partitioned parallelism on multicore CPUs. Other algorithms: BRISK, FAST, ORB, HARRIS, GFTT, SimpleBlob and SIFT, do not correlate to L3-cache in the same extent, and they are therefore more suitable for data-partitioned parallelism. Furthermore, the SIFT algorithm provides the most stable speed-up, resulting in an execution between 3 and 3.5 times faster than the original execution time for all image sizes. We also have evaluated the hardware resource usage by measuring the algorithm execution time simultaneously with the L3-cache usage. We have used our measurements to conclude which algorithms are suitable for parallelization on hardware with shared resources.

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Platforms with different computation resource, e.g. CPUs and FPGAs, become one of the first choices to deploy performance-requiring embedded applications. On this technology, functionalities can be implemented either as hardware (HW) or software (SW) components. Here, we extend the MultiPar methodology to support the selection of optimal partitioning solutions with respect to system properties. We show the feasibility of the proposed methodology and validate the composition rules for properties used in the partitioning decision process.

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The complexity of modern embedded systems most often requires multiple specialized tools to be used during the development process. These tools are commonly integrated into tool chains. An efficient way of achieving such integration is through the use of an tool integration framework, with one of the most prominent of such frameworks being Open Services for Lifecycle Collaboration (OSLC). However, at present time OSLC does not provide an established way for fully integrating version control systems. This paper presents how version control systems can be integrated into a tool chain based on OSLC. The integration is enabled by defining a version control domain based on the OSLC core specification, describing how to represent versioned artifacts and perform version control operations. The proposed approach is implemented and its feasibility is proven on a case study tool chain, which integrates the Team Foundation Server version control system and an industrial design tool for the power distribution domain.

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Cyber-Physical Systems, building on embedded systems and ICT are large complex systems that pose challenges at multiple stages, out of which we mention here design, ownership and utilization. These systems are more and more penetrating our every-day life, impacting on multiple aspects of our activities. In spite of their complexity, or due to that, these systems are offering new opportunities for improving the quality of our lives, simplify our work while helping us to improve the results, and provide support for longer life-spans.

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Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, a cluster based processing core protection technique for NoC systems using PVS approach is presented. In case of network level faults, the processing core of faulty node can use any other router in the cluster for transmission or reception of data packets with proposed architecture. Simulation results show significant reduction in average packet latency at the expense of negligible area overhead.

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, we present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5̅×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

This paper presents a novel virtual-channel (VC) sharing technique for NoC architecture. The proposed architecture improves the utilization of resources to enhance the performance with minimal overheads. A heuristic approach towards the proper VC sharing strategy is proposed, which is performed by an adaptive algorithm that configures the VC sharing based on link load parameters. Architectural design to realize the adaptive VC sharing in generic router is elaborated. The technique can be applied to any NoC architecture, including 3-D NoCs. Extensive quantitative experiments with synthetic and real benchmarks, including an integrated video conference application, demonstrate considerable improvement in area and power efficiency compared to existing VC-based 2D/3D NoC architectures.

Reliability of embedded systems and devices is becoming a challenge with technology scaling. To deal with the reliability issues, fault tolerant solutions are needed. The design paradigm for future System-on-Chip (SoC) implementation is Network-on-Chip (NoC). Fault tolerance in NoC can be achieved at many abstraction levels. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. In this paper, we propose a NoC architecture, which sustains the overall system performance by utilizing resources, which cannot be used by other architectures under faults. An approach towards a proper virtual-channel (VC) sharing strategy is proposed, based on communication bandwidth requirements. The technique can be applied to any NoC architecture, including 3-D NoCs. Extensive quantitative experiments with synthetic benchmarks, including uniform, transpose and negative exponential distribution (NED), demonstrate considerable improvement in terms of performance sustainability under faulty conditions compared to existing VC-based NoC architectures.

A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead. We propose sharing the VC buffers among dual inputs, which provides the performance advantage as conventional VC-based router with minimized overhead. We reason theoretically and demonstrate quantitatively the benefits of proposed architecture by comparing to state-of-the-art NoC routers, with various traffic patterns. Extensive experiments with synthetic and real benchmarks show significant area and power saving with similar performance compared to latest VC based NoC architectures.

We analyze here the topic of integration, in the area of process automation, from sensor/actuator levels to plant management levels. The communication at fieldbus level is based on wireless technology while management applications run in wired control systems, but can also be distributed, communicating via the Internet. This work aims at building a real-life demonstrator at Boliden, a mining and smelting plant located in Boliden, Sweden. A small process control environment is to be deployed at the plant to supervise a tank level control system. Targeted results are an interface between wireless and wired systems, the deployment of a wireless process control environment at Boliden, and the development of the enterprise business management facilities.

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We discuss a design methodology for SegBus, a multicore segmented bus platform. The methodology supports the modeling of the platform at several abstraction levels, enabling the designer to focus only on the relevant aspects of the architecture at a given development stage. We employ the unified modeling language (UML) as a specification language for theSegBusplatform and we customize its elements to serve our specific purposes via the profiling mechanism. The approach enables us to take advantage of graphical models of the platform and of automated refinements of these models towards implementation.

In this paper, we approach the definition of design methodologies for on-chip distributed platforms. The focus is on one segmented bus approach, the SegBus platform. The approach suggests the creation of a Unified Modeling Language (UML) profile that will allow a unified representation of both platform and application

A major challenge in the design of any real time system is the proper selection of implementation and platform alternatives. In this paper, a suitable FPGA-based design of the H.264 decoder is presented. Since H.264 standard only specifies the syntax and semantics of the video stream and not the video codec itself, the selection process may be directed based upon the temporal complexity of different parts of the decoder. Here, we present the process flow of these parts using basic algebraic operators. The analysis of the required logic elements to implement the decoder, on various platforms, is presented

In this paper we demonstrate how to use action systems to specify and refine self-adaptive systems. Focusing on the special case in which there is a fixed set of possible configurations, we use a recently-introduced synchronization operator to achieve separation of concerns between adaptation policy and steady-state system execution. The use of action systems permits the application of standard techniques for refinement to construct correct implementations from higher-level models. We illustrate the application of this idea to the problem of coping with dynamically-varying user requirements.

We concentrate on two major aspects of reactive system design: behavior control and modularity. These are studied from a formal point of view, within the framework of action systems. The traditional interleaving paradigm is completed with a new barrier synchronization mechanism. This is achieved by introducing a new parallel composition operator, applicable to both discrete and hybrid models. While offering improvements with respect to control and modularity, the approach uses the correctness preserving mechanisms provided by the underlying reasoning environment.

This study shows the derivation of a local segmented bus arbiter from an original single segment bus arbiter. The operations are performed in the formal framework of action systems and illustrated in a graphical manner using the corresponding action systems - UML profile notations. The derivation is useful both to demonstrate the capability of preserving correctness when considering an important hardware design decision and also to identify means through which this kind of decisions can be performed in a graphical environment.