This paper presents a method for thread partitioning for a hardware compiler Bach.Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel.The system description is decomposed into threads, i.e., strings of sequential processes, and then converted into synthesizable behavioral VHDL models.The proposed method attempts to find a partitioning of a given system description into threads that maximize resource sharing among processes in the threads.Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%.We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from a behavioral Bach-C description and statically prescheduled to synchronize communications between threads if possible. Then all the operations and communications of each thread are synthesized independently according to the prescheduling result. Consequently, we can synthesize large system LSIs efficiently, because we do not need to synthesize the whole system descriptions at once to synchronize communications. Experimental results show that our method improves throughput of synthesized circuits and is applicable to large systems designed with the Bach hardware compiler.

As a new approach for timing verification of logic circuits, we propose a new concept of time-symbolic simulation. While a conventional symbolic simulator treats signal values as logical expressions, a time-symbolic simulator treats time as algebraic expressions. In this paper, we describe algorithms for time-symbolic simulation, and its application to hazard detection and verification of asynchronous sequential circuits.