Abstract The 2D mesh topology-based Network-on-Chip (NoC) is a prevalent structure in System-on-Chip (SoC) designs, offering implementation and fabrication benefits. However, increased NoC scale leads to longer communication paths, more hops, and higher end-to-end latency and energy consumption. To mitigate these issues, Wireless NoC (WiNoC) integrates wireless communication, enhancing data rates, energy efficiency, and routing flexibility. Despite several mapping algorithms for NoCs, optimal techniques for hybrid WiNoCs are underexplored. This study proposes two novel application mapping methods for 2D mesh topology-based hybrid WiNoCs, using quadratic programming (QP) and simulated annealing (SA). Our goal is to minimize communication-related energy consumption. We evaluated these methods across various wireless router configurations, benchmarks, and custom application graphs. The QP-based method excels in smaller problems, while the SA-based approach yields optimal or near-optimal results for larger sizes within practical runtimes.

Abstract The number of Internet-of-Things (IoT) devices has been increasing rapidly every year. Most of these devices have access to important personal data such as health, daily activities, location, and finance. However, these devices have security problems since they have limited processing power and memory to implement complex security measures. Therefore, they possess weak authentication mechanisms and a lack of encryption. Additionally, there are no widely accepted standards for IoT security. Device Identifier Composition Engine (DICE) was proposed as a standard that enables adding a security layer to low-cost microcontrollers with minimal silicon overhead. However, previous studies show that DICE-based attestation is vulnerable to some remote attacks. In this study, we present a novel method called DICEguard to address the security problems of DICE. One of the key innovations of DICEguard is its incorporation of periodic memory forensics (PMF) technique, leveraging a hardware-based hash engine to detect and mitigate potential security breaches resulting from firmware vulnerabilities. DICEguard enhances the overall resilience of IoT devices against attacks by swiftly detecting alterations indicative of malicious activity through periodic calculation and comparison of firmware digests. Furthermore, DICEguard introduces a one-time programmable (OTP) memory component to safeguard critical security parameters, such as public keys used for signature verification, against tampering by adversaries. This ensures the integrity of essential security measures even in the face of sophisticated attacks. We implemented the enhanced DICE architecture using the open-source RISC-V platform Ibex and the mbedTLS library for cryptographic operations. We performed the hash operations required by DICE in a hardware-based manner on a commercial Field Programmable Gate Array (FPGA) platform rather than firmware, which is more vulnerable to attacks. Our test results show that with negligible area overhead to a standard microcontroller system, the proposed method can detect the simulated attacks.

Quality of Service (QoS) within the Internet of Things (IoT) by facilitating decentralized processing and bringing the computation and storage resources closer to the network edge. It reduces the latency of application responses to the end-users when compared to the cloud computing only-based approaches. One of the major challenges that hinder the ubiquitous adoption of IoT technologies is the efficient handling of resource allocation. There is a necessity for a smart layer that would facilitate efficient and adaptive scheduling between the edge and fog nodes, especially in light of the dynamic and heterogeneous nature of today's fog/cloud-based IoT systems. In this study, we present a theoretical model for such an intermediary layer middleware, with an objective to enable QoS-aware allocation of fog resources.

Shrinking technology sizes of the CMOS circuits makes it possible to place more transistors on a single chip at each technology generation. On the other hand, circuits become more vulnerable to radiation effects due to lower supply and threshold voltage levels; thus, the number of transient faults in circuits tends to increase. Moreover, energy reduction techniques also negatively affect the reliability of circuits. Traditional high-level synthesis (HLS) methods usually consider only area and latency along with either energy or reliability. Especially the effect of using different voltage levels on reliability is completely ignored by previous studies. In this article, we present two new HLS methods for application-specific integrated circuit (ASIC) design under area and timing constraints with the objectives of low energy consumption and high reliability. For the mapping and scheduling steps of HLS, we propose integer linear programming (ILP) and genetic algorithm (GA)-based optimization methods. While ILP provides the optimum results, the CPU time increases exponentially with the number of application nodes. On the other hand, GA-based metaheuristic is faster and determines optimum or near-optimum results in shorter times than ILP. Additionally, we use a selective duplication method to further improve the overall reliability.

The aim of most Internet of Things (IoT) networks is to allow different devices with various capabilities to share their resources and cooperate to perform a demanded task. Most of IoT objects are heterogeneous and are equipped with limited energy and computational capabilities. Therefore, distributing tasks to these objects represents a big challenge. In the literature, most of the existing works use heuristic optimizations to deal with different aspects of task allocation problem without considering the heterogeneity nature of the objects and the effect of their limited resources. In this paper, we first model the problem of task allocation in Internet of Things by adopting the concept of task groups and virtual objects. Then, we develop a multi-objective optimization algorithm to solve the task allocation problem. The algorithm simultaneously optimizes two contradictory objectives: computational power and energy efficiency. The first objective considers the fact that virtual objects are the basic units of computations and attempts to maximize the mean value of the computational power of virtual objects. On the other hand, the second objective aims to minimize the total dissipated energy in the network to ensure maximum operational and stability periods. In order to verify and test the effectiveness of the proposed algorithm, we performed extensive MATLAB based analysis as well as application layer simulations, based on OMNeT++, with various scenarios and compared our results with the most relevant algorithm in the literature.

New communication methods have become inevitable due to the continuous increase in the number of components on the integrated circuits. Network-on-Chip (NoC) meets this need with its scalability and parallelism features. Furthermore, 3D-NoC architecture has been developed due to more speed and less power consumption demands. However, the routing problem for 3D becomes more complicated. Since deterministic algorithms frequently encounter congestion problems, adaptive algorithms give better results considering the system's traffic load. Motivated by the effectiveness of learning algorithms on this type of problems, we present a Q-Learning based routing algorithm for the 3D-NoC routing problem. In our algorithm, each router node maintains a Q-Table and updates it by receiving the traffic information from neighboring routers. We select the output port of the packets coming to the node according to this table. We compared our method with the deterministic XYZ algorithm with different traffic models. The results show that our method achieved 8% performance improvement.

Abstract Learning‐based routing algorithms are good candidates for two‐dimensional Network‐on‐Chip (NoC) architectures since they can give good path selection decisions by combining current and past state of the network traffic. On the other hand, they generally send packets through nonminimal paths in order to detour congested areas in an attempt to minimize the communication cost. Since adapting to the traffic changes takes time to gather enough feedback information by the applied learning model, non‐minimal paths may take more time than the congested minimal paths. In this work, we incorporate a probabilistic method to a Q‐learning‐based NoC routing algorithm for selecting a minimal or nonminimal path to minimize the negative effect of learning duration. We also consider the errors in the architecture and propose a fault‐tolerance mechanism that detects both transient and permanent link errors. We compared our method against a standard Q‐learning‐based routing algorithm on several traffic models in terms of throughput and latency. The results show that our method outperforms its counterpart up to 30% in latency and 7% in throughput.

Rapidly decreasing size of the CMOS transistors allowed us to place more components on a single chip than ever before. In order to meet the performance demands of these dense designs, designers introduced an efficient communication paradigm, Network-on-Chip (NoC), instead of traditional wiring-based methods. Although mesh topology is most commonly used topology for NoC design, it has several problems such as network congestion and energy consumption. Reconfigurable mesh topology is a good alternative to traditional mesh since it gives more mapping and routing options for reducing network congestion. However, design automation tools still lack efficient mapping and routing algorithms for reconfigurable meshes. In this study, we propose a genetic algorithm (GA) based method that simultaneously maps the application nodes on 2D reconfigurable mesh structure and determines the routing paths between communicating pairs with the objective of energy minimization. We have applied our method on four benchmarks and compared our results against two heuristic strategies. Simulation results show the superiority of our proposed method over the existing ones in terms of energy consumption.

In telecommunication systems, if there is a call (voice or short message) from one operator to another, the called number must be analyzed to determine its destination operator and to check if it has enough credit to start this call. This process must be very fast to reduce the switching cost of the call. Considering the dynamically updated number portability list and bulk calls, the number analysis process may take too much time, resulting in call drops. In this study, we present a number analysis system that is developed in order to start bulk calls in the fastest way. The developed system is able to detect the operators of the numbers by scanning both the continuously updated number potability list and the number data base having a large number of entries. In our experiments, we compared the proposed method with the classical relational database inquiry methods in terms of response times. We achieved 177X speed up for the analysis of thousand numbers. Reducing the number analysis times brought significant reductions in forwarding costs.

Network-on-Chip (NoC) is a promising approach for supporting heavy communication demand among the parts of modern high-performance nanoscale System-on-Chips (SoCs). Three-dimensional integration (3D) for integrated circuits (ICs) has become popular since it reduces the latency and energy consumption by replacing long global interconnects with short vertical through-silicon-via (TSV) interconnects between stacked dies. Combining NoCs with 3D technology seems a good choice for achieving better performances than 2D. Although there are good synthesis methods for energy- and communication-aware 2D-NoC design, we lack the 3D alternatives. Motivated by the needs, in this paper, we propose an energy-aware application-specific topology generation method for 3D-NoCs. Our method is based on a heuristic optimization algorithm that partitions the application nodes among layers of the NoC architecture with an attempt to minimize the dynamic energy consumption. We tested our 3D method against a 2D alternative through several NoC benchmarks. Simulation results show that our approach brings huge energy and area savings against its 2D counterpart.

Combinational circuits have become more vulnerable to soft errors (SEs) in each CMOS technology generation. Most of the prior studies use hardware redundancy in an attempt to harden the circuits against errors. However, redundancy increases the area and power consumption. Furthermore, the design constraints may not allow adding redundant resources to the final circuit. In this paper, we present a genetic algorithm (GA)-based design method to increase the reliability of combinational circuits. In this method, we use different versions of the same resources, each having different area, latency, and reliability values. The goal of GA-based method is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 19.90% (14.50% on average) reliability improvement against a heuristic method with no additional area overhead.

As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.

As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this study, we aim to make faulty chips designed with Network-on-Chip (NoC) communication usable. Specifically, we present a fault-tolerant irregular topology generation method for application specific NoC designs. Designed NoC topology allows a different routing path if there is a link failure on the default routing. We compare fault-tolerant topologies with regular fault-tolerant ring topologies, and non-fault-tolerant application specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs.

One of the most important problems in resource-constrained embedded systems is limited memory space for code and data. This paper targets at DSP based architectures and proposes an ILP (integer linear programming) based approach for reducing code memory space requirements by exploiting the auto-increment and auto-decrement addressing modes provided by DSPs. Specifically, we address the problem of effective use of address registers, demonstrate how we can take advantage of additional capabilities that exists in some recent DSPs (such as modify registers), and discuss how our ILP-based solution can be used for performing tradeoffs between code memory and data memory space requirements. We also compare our approach to a previously-proposed heuristic solution. Our experimental analysis using several applications indicate that the proposed ILP-based approach is very effective in reducing both code memory demand and execution cycles, and the solution times it takes are within tolerable limits.

The importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density circuits, and employment of power-saving techniques such as voltage scaling and component shut-down. As a result, it is becoming necessary to treat reliability as a first-class citizen in system design. In particular, reliability decisions taken early in system design can have significant benefits in terms of design quality. Motivated by this observation, this paper presents a reliability-centric high-level synthesis approach that addresses the soft error problem. The proposed approach tries to maximize reliability of the design while observing the bounds on area and performance, and makes use of our reliability characterization of hardware components such as adders and multipliers. We implemented the proposed approach, performed experiments with several designs, and compared the results with those obtained by a prior proposal.