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Kouichi Honma

dblp:29/4849 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2Artificial intelligence and machine learning · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Audio and music processing · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Audio and music processing › speech coding
adaptive predictive coding		 0.011988
APC-AB codec modules operating at 16 and 8 kbit/s · IEEE J. Sel. Areas Commun. 1988
Audio and music processing
speech coding		 0.011988
APC-AB codec modules operating at 16 and 8 kbit/s · IEEE J. Sel. Areas Commun. 1988
Integrated circuit design › digital signal processing circuits
digital signal processor design		 0.011988
APC-AB codec modules operating at 16 and 8 kbit/s · IEEE J. Sel. Areas Commun. 1988

Methods — techniques the papers use, named apart from their topics

adaptive bit allocation · 0.0APC-AB algorithm · 0.0
YearPublicationVenuePosition
2005 Design of bandwidth scalable LSF quantization using interframe and intraframe prediction
Hiroyuki Ehara, Toshiyuki Morii, Masahiro Oshikiri, Koji Yoshida, Kouichi Honma
 INTERSPEECH5
1988 APC-AB codec modules operating at 16 and 8 kbit/s
abstract
High-quality speech codec modules operating at 16 and 8 kb/s have been developed using an adaptive predictive coding with adaptive bit allocation (APC-AB) scheme. An optimized APC-AB algorithm is studied that reduces processing complexity while maintaining speech quality. The coding algorithm is implemented in two digital signal processors (DSPs). The DSP chips, a framing LSI circuit, a PCM codec, and some peripheral ICs are integrated in each of two compact packages, i.e. codec modules, operating at 16 or 8 kb/s. The codec module size is as small as 80 mm*50 mm*12 mm, and its typical power consumption is 500 mW using 2- mu m CMOS LSI technology. At 16 kb/s this APC-AB codec achieves high speech quality, close to that of a 7-bit mu -law PCM. The codec modules are expected to be used for various applications such as customer premises multiplexers for digital leased lines, digital mobile radio, and stored-and-forward-message systems (voice-mail systems).>
Kazunori Irie, Yasuhiko Tada, Kouichi Honma
 IEEE J. Sel. Areas Commun.3
1986 16 kbit/s APC/AB Coder Using a Single Chip Digital Signal Processor
Yasuhiko Tada, Masahiro Taka, Kouichi Honma
 ICC3