Arun Kannan

dblp:29/4882 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 67% Energy-efficient computing · 33%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › power management
processor power reduction
0.112009
A Software-Only Solution to Use Scratch Pads for Stack Data · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Memory systems › on-chip memory
scratchpad memory
0.112009
A Software-Only Solution to Use Scratch Pads for Stack Data · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Memory systems › memory management
stack data management
0.112009
A Software-Only Solution to Use Scratch Pads for Stack Data · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Operating systems › resource management
memory management
0.012009
A Software-Only Solution to Use Scratch Pads for Stack Data · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009

Methods — techniques the papers use, named apart from their topics

software SPM management · 0.2
YearPublicationVenuePosition
2009 A software solution for dynamic stack management on scratch pad memory
abstract
In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. However, application mapping on SPMs remain a challenge. We propose a dynamic SPM management scheme for program stack data for processor power reduction. As opposed to previous efforts, our solution does not mandate any hardware changes, does not need profile information, and SPM size at compile-time, and seamlessly integrates support for recursive functions. Our technique manages stack frames on SPM using a scratch pad memory manager (SPMM), integrated into the application binary by the compiler. Our experiments on benchmarks from MiBench show average energy savings of 37% along with a performance improvement of 18%.
Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jongeun Lee
ASP-DAC1
2009 A Software-Only Solution to Use Scratch Pads for Stack Data
abstract
A dynamic scratch pad memory (SPM) management scheme for program stack data with the objective of processor power reduction is presented. Basic technique does not need the SPM size at compile time, does not mandate any hardware changes, does not need profile information, and seamlessly integrates support for recursive functions. Stack frames are managed using a software SPM manager, integrated into the application binary, and shows average energy savings of 32% along with a performance improvement of 13%, on benchmarks from MiBench. SPM management can be further optimized and made pointer safe, by knowing the SPM size.
Aviral Shrivastava, Arun Kannan, Jongeun Lee
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2008 SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories
Amit Pabalkar, Aviral Shrivastava, Arun Kannan, Jongeun Lee
HiPC3