Spin-transfer torque magnetic memory (STT-MRAM) has gained significant research interest due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent integration density, acceptable read and write performance, and compatibility with CMOS process technology. However, several obstacles need to be overcome for STT-MRAM to become the universal memory technology. This paper first reviews the fundamentals of STT-MRAM and discusses key experimental breakthroughs. The state of the art in STT-MRAM is then discussed, beginning with the device design concepts and challenges. The corresponding bit-cell design solutions are also presented, followed by the STT-MRAM cache architectures suitable for on-chip applications.

As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments have shown that a nano-magnet can be switched by a spin-polarized current and this has led to a number of novel device proposals over the past few years. In this paper, we provide a review of different mechanisms that manipulate the state of a nano-magnet using current-induced spin-transfer torque and demonstrate how such mechanisms have been engineered to develop device structures for energy-efficient on-chip memory and logic.

The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM bit-cells under process variations: the bit-cells need to be significantly upsized to improve bit-cell failure, resulting in increased bit-cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM bit-cells with improved yield, namely, bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-cells designed with word-line boosting for write has a bit-cell area reduced by > 75% at iso-failure probability, compared to bit-cells without any failure mitigation technique. When bit-cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by 15% , compared to bit-cells designed without failure mitigation techniques.

Spin-transfer torque magnetic RAM (STT-MRAM) is a promising memory technology for lower level caches because of its high density and nonvolatile nature. However, the high write latency is a bottleneck to its widespread adoption as the future on-chip memory. In this paper, we propose a new cache architecture-asymmetric write architecture with redundant blocks (AWARE)-that can improve the write latency by taking advantage of the asymmetric write characteristics of 1T-1MTJ STT-MRAM bit-cells. Due to the nature of the storage element in STT-MRAM, the time required for the two-state transitions ( 1→ 0 and 0→ 1) is not identical. In other words, one of the state transitions is slower than the other direction. In conventional cache architecture, the overall write latency is limited by the slower transition. However, the AWARE cache design introduces redundant blocks in each row, and they are preset to the initial state that enables the faster transition. Hence the write operations performed in these redundant blocks are much faster than the conventional write scheme. The write latency in AWARE is improved by 30% over conventional cache architecture with no area penalty in the data array. Moreover, the additional tag bits introduced in this technique result in penalty on the total cache area. In addition, the write energy increases modestly by 7% in the proposed cache design. However, this write-energy increase can be mitigated by sacrificing the cache capacity.

Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical.