This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto field-programmable gate arrays (FPGAs). This paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer. Experimental results are reported on a set of eight MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.

This paper presents a detailed evaluation of parallel mesaagedriven pmgmms on both message-passing and shared memory pamllel architectures.Four large pomllel appiications from the domain of VLSI computer aided design are evaluated, namely: parallel test pattern genemtion, pamllel cell placement, logic qnthesis, and event dn'ven VHDL kmulalion.The parallelism structure, the communication characterktics, locality chamcterirrtics, gmin sizes of wmputationa, and detailed measurement8 of system time, idle time, and uaer time are meaaunzd for theae applicationa.Resulta are presented for an Intel Pamgon distributed-memory measagepassing multicomputer and compared to a Sun SPARCcenter 1 OOOE symmetric multiprocessor.

Simulated annealing, a methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm and, as such, numerous researchers have undertaken efforts to parallelize it. In this paper, we investigate three of these parallel simulated annealing strategies when applied to standard cell placement, specifically the TimberWolfSC placement tool. We have examined a parallel moves strategy, as well as two new approaches to parallel cell placement-multiple Markov chains and speculative computation. These algorithms have been implemented in ProperPLACE, our parallel cell placement application, as part of the ProperCAD II project. We have constructed ProperPLACE so that it is portable across a wide range of parallel architectures. Our parallel moves algorithm uses novel approaches to dynamic message sizing, message prioritization, and error control. We show that parallel moves and multiple Markov chains are effective approaches to parallel simulated annealing when applied to TimberWolfSC, yet speculative computation is wholly inadequate.

Fault simulation for sequential circuits numbers among the highly compute intensive tasks in the integrated circuit design process. In the quest for rapid design turn around, parallelization has been proposed to speed fault simulation. We introduce ProperPROOFS, a parallel extension of the PROOFS fault simulation package. ProperPROOFS exploits parallelism based on fault partitioning, incorporating static and dynamic partitioning schemes and a new asynchronous and distributed method of fault redistribution. We present results for circuits in the ISCAS-89 benchmark set across several parallel architectures. A detailed evaluation of results provides new insight into the use of fault partitioning to parallelize high performance serial fault simulation applications.

Automatic test pattern generation (ATPG) for sequential circuits remains one of the most compute-intensive tasks in the integrated circuit design process. Although numerous attempts have been made to speed the ATPG process via parallelization, these attempts have often proved disappointing when compared against the best available serial algorithms using metrics of resultant quality and performance. In this paper we introduce ProperHITEC, a parallel extension of the HITEC/PROOFS sequential test generation package. ProperHITEC embodies a new approach to parallel ATPG; it is incrementally derived from one of the best-performing serial algorithms and this incremental derivation is implemented via the mechanisms of object-oriented programming. Results of running ProperHITEC on three parallel architectures, the Sun 4/600MP, the INTEL iPSC/860, and the Encore Multimax are presented. These results show that ProperHITEC achieves results virtually identical in quality to HITEC while achieving significant multiprocessor utilization.

The use of parallel platforms, despite their increasing availability, remains largely restricted to well-structured, numeric applications. We address the issue of facilitating the use of parallel platforms on unstructured problems through object-oriented design techniques and the actor model of concurrent computation. We present a multi-level approach to expressing parallelism for unstructured applications: a high-level interface based on the actor model of concurrent object-oriented programming and a low-level interface which provides an object-oriented interface to system services across a wide range of parallel architectures. The high- and low-level interfaces are implemented as part of the ProperCAD II C++ class library which supports shared memory, message-passing, and and hybrid architectures. We demonstrate our approach through a detailed examination of the parallelization process for an existing unstructured serial application, viz. a state-of-the-art VLSI computer-aided design application. We compare and contrast the library-based actor approach to other method for expressing parallelism in C++ on a number of applications and kernels.>