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G. Persky

dblp:29/5267 · DBLP profile ↗
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5ranked-venue papers
5as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 5 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Electronic design automation · 100%
Theoretical computer science
1 paper
Graph algorithms and graph theory · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.051984
Topological routing of multi-bit data buses · DAC 1984
Comments on "An Optimal Solution for the Channel-Assignment Problem" · IEEE Trans. Computers 1981
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing · DAC 1981
Electronic design automation › physical design
routing
0.041984
Topological routing of multi-bit data buses · DAC 1984
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing · DAC 1981
LTX - a system for the directed automatic design of LSI circuits · DAC 1976
Electronic design automation › physical design › routing
channel routing
0.041981
Comments on "An Optimal Solution for the Channel-Assignment Problem" · IEEE Trans. Computers 1981
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing · DAC 1981
LTX - a system for the directed automatic design of LSI circuits · DAC 1976
Electronic design automation › physical design › routing › VLSI routing
topological routing
0.011984
Topological routing of multi-bit data buses · DAC 1984
Electronic design automation › physical design
placement
0.021976
LTX - a system for the directed automatic design of LSI circuits · DAC 1976
PRO - an automatic string placement program for polycell layout · DAC 1976
Electronic design automation › physical design › placement › circuit placement
two-dimensional placement
0.011976
LTX - a system for the directed automatic design of LSI circuits · DAC 1976
Graph algorithms and graph theory
graph algorithms
0.011981
Comments on "An Optimal Solution for the Channel-Assignment Problem" · IEEE Trans. Computers 1981

Methods — techniques the papers use, named apart from their topics

pairwise neighbor exchange · 0.0interactive layout procedures · 0.0cell reflection · 0.0automatic layout procedures · 0.0
YearPublicationVenuePosition
1984 Topological routing of multi-bit data buses
G. Persky, L. V. Tran
DAC1
1981 The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
G. Persky, C. Enger, Matthew Selove
DAC1
1981 Comments on "An Optimal Solution for the Channel-Assignment Problem"
abstract
The main thrust of the above paper1appears to be a detailed restatement of the "left-edge algorithm" [1], [2] for channel routing. This algorithm is almost a decade old and is now quite familiar to most workers in the field of LSI design automation. That the authors did not reference this earlier work, and devoted much of their paper to a reexposition certainly detracts from its usefulness.
G. Persky, Bou Nin Tien, Ben Ting
IEEE Trans. Computers1
1976 PRO - an automatic string placement program for polycell layout
abstract
This paper describes an automatic string placement program used to reorder cells in polycell rows such that channel routing in the adjacent channels (a) is not blocked by cyclic constraints, and (b) needs fewer routing tracks. The program utilizes cell reflections and pairwise neighbor exchanges, simultaneously monitoring both the channels immediately above and below the row being reordered. Reductions of 25% in the number of required routing tracks are commonly obtained.
G. Persky
DAC1
1976 LTX - a system for the directed automatic design of LSI circuits
abstract
LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms for two-dimensional placement, string placement, exploitation of equivalent terminals, decomposition of routing into channels, and channel routing. Circuit connectivity is preserved during interactive procedures. LTX runs on an H-P 2100 series computer with 32K of memory and disc.
G. Persky, David N. Deutsch, Daniel G. Schweikert
DAC1