For perception systems in mobile robotics - particularly in demanding, highly dynamic environments - event cameras (DVS - Dynamic Vision Sensors) are being increasingly utilised as an alternative to conventional vision sensors. The real-time processing of the registered spatio-temporal sparse point cloud must satisfy stringent requirements in terms of latency, throughput, and energy efficiency. In this demonstration, we present our method for implementing Graph Convolutional Neural Networks on a heterogeneous SoC FPGA platform, aimed at meeting these constraints. We address the challenges associated with integrating event-based sensors with reconfigurable hardware, as well as the intricate relationship between latency, performance, and hardware resource utilisation.

The performance of object detection systems in automotive solutions must be as high as possible, with minimal response time and, due to the often battery-powered operation, low energy consumption. When designing such solutions, we therefore face challenges typical for embedded vision systems: the problem of fitting algorithms of high memory and computational complexity into small low-power devices. In this paper we propose PowerYOLO - a mixed precision solution, which targets three essential elements of such application. First, we propose a system based on a Dynamic Vision Sensor (DVS), a novel sensor, that offers low power requirements and operates well in conditions with variable illumination. It is these features that may make event cameras a preferential choice over frame cameras in some applications. Second, to ensure high accuracy and low memory and computational complexity, we propose to use 4-bit width Powers-of- Two (PoT) quantisation for convolution weights of the YOLO detector, with all other parameters quantised linearly. Finally, we embrace from PoT scheme and replace multiplication with bit-shifting to increase the efficiency of hardware acceleration of such solution, with a special convolution-batch normalisation fusion scheme. The use of specific sensor with PoT quantisation and special batch normalisation fusion leads to a unique system with almost 8x reduction in memory complexity and vast computational simplifications, with relation to a standard approach. This efficient system achieves high accuracy of mAP 0.301 on the GENt DVS dataset, marking the new state-of-the-art for such compressed model.

In this demo, we present a hardware-software system for 3D object detection in LiDAR point clouds based on a deep neural network. The PointPillars architecture was used in this research, as it is a reasonable compromise between detection accuracy and computational complexity. The Brevitas tool was used for network quantisation and the FINN tool for hardware-software implementation in the reprogrammable Zynq UltraScale+ MPSoC device.

High Efficiency Video Coding (HEVC), a modern video compression standard, exceeds the predecessor H.264 in efficiency by 50%, but with cost of increased complexity.It is one of main research topics for FPGA engineers working on image compression algorithms.On the other hand high-level synthesis tools after few years of lower interest from the industry and academic research, started to gain more of it recently.This paper presents FPGA implementation of HEVC 2D Inverse DCT transform implemented on Xilinx Virtex-6 using Impulse C high level language.Achieved results exceed 1080p@30fps with relatively high FPGA clock frequency and moderate resource usage.

Object detection and localization in a video stream is an important requirement for almost all vision systems. In the article a design embedded into a reconfigurable device which is using the Histogram of Oriented Gradients for feature extraction and SVM classification for detecting multiple objects is presented. Superior accuracy is achieved by making all computations using single precision 32-bit floating point values in all stages of image processing. The resulting implementation is fully pipelined and there is no need for external memory. Finally a working system able to detect and localize three different classes of objects in color images with resolution 640×480 @ 60fps is presented with a computational performance above 9 GFLOPS.

The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version of the algorithm and verifies its operation on two FPGA cards in practice. On the basis of one of these cards, the article proposes a prototype of an effective supercomputer-compatible hardware accelerator (High Performance Computing Application).

In the present paper the background generation and motion detection algorithms, which are of key importance for the implementation of videodetection, have been presented. A modification of the background generation algorithm, essential for proper algorithm functioning at medium and high road-traffic conditions, has been proposed. Algorithm adaptation for the implementation in reprogrammable device has been also presented. A modification of the SAD algorithm, used in motion detection, has been introduced. The modification allows for regions of interest of irregular shape and structure in the analyzed image. It creates a capability to conduct the calculations in independent and parallel manner for specific, user-defined, active videodetection regions. PixelStream-based implementation has been successfully performed. Real-time verification on reconfigurable platform has been done.

In the present paper the background generation and motion detection algorithms, which are of key importance for the implementation of video detection, have been presented. A modification of the background generation algorithm, essential for proper algorithm functioning at medium and high road-traffic conditions, has been proposed. Algorithm adaptation for the implementation in reprogrammable device has been also presented. PixelStream-based implementation has been successfully performed. Real-time verification on reconfigurable platform has been done.

In the paper, an FPGA realization is described for a DV decoder, working in real-time with digital signal conformant to IEC-6 1834-2 standard. The FPGA decoder covers the following stages of the signal decompression: Inverse VLC, Inverse Quantization, Inverse Weighting, Inverse DCT and all the auxiliary operations. Each stage of the operation has been realized by creation of processing element, based on the function codes implemented in Handel-C language. In order to achieve a real-time performance, optimization has been carried out for algorithms and all function codes. Next, a pipeline implementation for the video stream has been completed. Finally, the function execution has been parallelized in the pipeline at the single video block level. Hardware-software test stand has been designed and set-up and then testing has been carried out on real data transmitted on-line from a DV camcorder.

In the paper the implementation of classical label component algorithm in Handel-C language has been discussed. The implementation of the image segmentation stage has been realized in real-time in the pipeline structure. The process of construction of optimal implementation has been shown, including the algorithm parallelization on one hand and taking advantage of the language features on the other. Each implementation has been verified in hardware and tested by a set of specially designed test images.

In the present paper construction of a controller is described, which is used to control the RETINA image processing platform. The 32-bit RETINA card is dedicated to be used for image acquisition, processing and analysis. The module resources include Video ADC, Virtex FPGA device, floating point Motorola 96002 DSP and PCI Master interface, what enables the execution of all the operations in real-time. Controller is the main control centre for the module, supervising the modes and phases of its operation, and it is also used as a arbiter for the module's communication resources.