Demo Data from EDBT 2026 / reviewers in the wild / expert
Kaushik Sheth
dblp:29/5320
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorArtificial intelligence and machine learning · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 77% Integrated circuit design · 23% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › system-level design
chip-package co-design |
0.1 | 1 | 2006 | The importance of adopting a package-aware chip design flow · DAC 2006 |
Electronic design automation
physical design |
0.1 | 1 | 2006 | The importance of adopting a package-aware chip design flow · DAC 2006 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 2006 | The importance of adopting a package-aware chip design flow · DAC 2006 |
Integrated circuit design
interconnect |
0.0 | 1 | 2006 | The importance of adopting a package-aware chip design flow · DAC 2006 |
Methods — techniques the papers use, named apart from their topics
simultaneous interconnect synthesis · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | The importance of adopting a package-aware chip design flowabstractIn this paper, we talk about the short- and long-term implications of ignoring the relationship between the chip, package and PCB during I/O planning and how these issues will manifest themselves as we move toward 65 and 45nm technology.It also introduces a whole new approach to chip/package I/O planning and optimization. This new approach simultaneously synthesizes the entire interconnect from the I/O driver to the package ball and establishes an interconnect plan that is optimized for both chip and package. Kaushik Sheth, Egino Sarto, Joel McGrath |
DAC | 1 |
| 2006 | A 3D Fax Machine based on ClaytronicsabstractThis paper presents a novel application of modular robotic technology. Many researchers expect manufacturing technology will allow robot modules to be built at smaller and smaller scales, but movement and actuation are increasingly difficult as dimensions shrink. We describe an application - a 3D fax machine - which exploits inter-module communication and computation without requiring self-reconfiguration. As a result, this application may be feasible sooner than applications which depend upon modules being able to move themselves. In our new approach to 3D faxing, a large number of submillimeter robot modules form an intelligent "clay" which can be reshaped via the external application of mechanical forces. This clay can act as a novel input device, using intermodule localization techniques to acquire the shape of a 3D object by casting. We describe software for such digital clay. We also describe how, when equipped with simple inter-module latches, such clay can be used as a 3D output device. Finally, we evaluate results from simulations which test how well our approach can replicate particular objects Padmanabhan Pillai, Jason Campbell, Gautam Kedia, Shishir Moudgal, Kaushik Sheth |
IROS | 5 |