The increase in routing table sizes, number of updates, traffic, speed of links and migration to IPv6 have made IP address lookup, based on longest prefix matching, a major bottleneck for high performance routers. We evaluate and compare several schemes based on complexity analysis and simulation results. We present a trie based scheme, which we call linked list cascade addressable trie (LLCAT), which is easy to be implemented in hardware and allows routing table update operations to be performed incrementally requiring very few memory operations guaranteed for worst case to satisfy requirements of dynamic routing tables in high speed routers. We also consider compression schemes to be applied to our algorithm to improve memory consumption and search time.

In this paper, we present a novel design of a large-scale multicast ATM switch. We first propose a basic switch architecture, where switch inputs and outputs are grouped into small modules called input shared blocks (ISB) and output shared blocks (OSB). Link sharing with round robin (RR) cell scheduling solves output contention and eliminates the speedup requirement for the central switch fabric. To support non-uniform traffic, an enhanced switch architecture with a round robin prioritized output link reservation algorithm (RR+POLR) is further introduced. Both RR and RR+POLR algorithms use a group mapping scheme and distribute input cells' contention resolution to every ISB. Scheduling complexity is dramatically reduced. Simulations for a 256/spl times/256 switch demonstrate an improved performance under non-uniform traffic.

Describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32/spl times/32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 /spl mu/m CMOS technology and tested to operate correctly at 240 MHz.

The asynchronous transfer mode (ATM) technique has been widely accepted as a flexible and effective scheme to transport various traffic over the future broadband network. To fully utilize network resources while still providing satisfactory quality of service (QOS) to all network users, prioritizing the user's traffic according to their service requirements becomes necessary. During call setup or service provisioning, each service can be assigned a service class determined by a delay priority and a loss priority. A queue manager in ATM network nodes will schedule ATM cells departing and discarding sequence based on their delay and loss priorities. Most queue management schemes proposed so far only consider either one of these two priority types. The queue manager handles multiple delay and loss priorities simultaneously. Moreover, a cell discarding strategy, called push-out, that allows the buffer to be completely shared by all service classes, has been adopted in the queue manager. We propose a practical architecture to implement the queue manager by using available VLSI sequencer chips.

This paper is concerned with the analysis and modeling of the effects of floating point quantization of subband signals in a two channel filter bank. It represents an extension of previous work for optimal fixed-point quantizers. In the present case, the quantization noise is modeled by a multiplicative noise as compared with additive noise representation for the fixed- point case. We derive equations for the autocorrelation and power spectral density (PSD) of the reconstructed signal y(n) in terms of the analysis/synthesis filters, the PSD of the input, and the quantizer model. Formulas for the mean-square error and for compaction gain are obtained in terms of these parameters. We assume the filter bank is perfect reconstruction (PR) (but not necessarily paraunitary) in the absence of quantization and transmission errors. The autocorrelation function of the output y(n) is generally non-stationary. However, it is cyclostationary since it is stationary when n is odd, or n is even; but not both. By taking the average of the autocorrelation for n even, and for n odd, we obtain a stationary autocorrelation, and its associated PSD. This cyclostationary analysis is used to compute the quantization noise component in the output, for any PR subband structure.