Neuromimetic algorithms, such as the HMAX algorithm, have been very successful in image classification tasks. However, current implementations of these algorithms do not scale well to large datasets. Often, target-specific features or patches are “learned” ahead of time and then correlated with test images during feature extraction. In this paper, we develop a novel method for selecting a single set of universal features that enables classification across a broad range of image classes. Our method trains multiple Random Forest classifiers using a large dictionary of features and then combines them using a majority voting scheme. This enables the selection of the most discriminative patches based on feature importance measures. Experiments demonstrate the viability of this method using HMAX features as well as the tradeoff between the number of universal features, classification performance, and processing time.

- neural connectivity maps of the brain-using the parallel execution of computer vision algorithms on high-performance compute clusters. These services and open-science data sets are publicly available at openconnecto.me. The system design inherits much from NoSQL scale-out and data-intensive computing architectures. We distribute data to cluster nodes by partitioning a spatial index. We direct I/O to different systems-reads to parallel disk arrays and writes to solid-state storage-to avoid I/O interference and maximize throughput. All programming interfaces are RESTful Web services, which are simple and stateless, improving scalability and usability. We include a performance evaluation of the production system, highlighting the effec-tiveness of spatial data organization.

This manuscript considers the following "graph classification" question: Given a collection of graphs and associated classes, how can one predict the class of a newly observed graph? To address this question, we propose a statistical model for graph/class pairs. This model naturally leads to a set of estimators to identify the class-conditional signal, or "signal-subgraph," defined as the collection of edges that are probabilistically different between the classes. The estimators admit classifiers which are asymptotically optimal and efficient, but which differ by their assumption about the "coherency" of the signal-subgraph (coherency is the extent to which the signal-edges "stick together" around a common subset of vertices). Via simulation, the best estimator is shown to be not just a function of the coherency of the model, but also the number of training samples. These estimators are employed to address a contemporary neuroscience question: Can we classify "connectomes" (brain-graphs) according to sex? The answer is yes, and significantly better than all benchmark algorithms considered. Synthetic data analysis demonstrates that even when the model is correct, given the relatively small number of training samples, the estimated signal-subgraph should be taken with a grain of salt. We conclude by discussing several possible extensions.

Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

We have developed a hardware and software platform, the WiiEMG, for controlling the Wii™ video game console with surface electromyography (EMG). WiiEMG is intended to assist with training and performance assessment of myoelectric control of upper arm prostheses. For this application, a player wears skin surface electrodes over myoelectric control sites. A real-time signal analysis system acquires amplified EMG signals and classifies the activity patterns associated with different motions. In addition, the amplitude of this pattern is used as a velocity signal, which is differentiated to give acceleration. Finally, a scaled version of this acceleration value is input as an analog voltage into a modified Wiimote™ in place of the normal accelerometer, and the Wiimote communicates the data to the console. To evaluate the system's performance, six able-bodied subjects were used to test the WiiEMG by playing the game Wii Tennis™ using myoelectric control. Results are reported that show how users develop improved EMG control after only a few brief trials. Improved muscle and EMG control has the potential to benefit myoelectric limb use as well as motor skills rehabilitation.

We study the dynamic control of ongoing loco-motor patterns through the application of discrete pulses of electrical stimulation to the central pattern generator (CPG) for locomotion. Data is presented from a hardware model of the CPG demonstrating that stimulation causes brief deviations from the CPG's limit cycle activity. It has been shown that the characteristics of the deviation depend strongly on the phase of stimulation. This paper expands upon those previous results in two ways. Firstly, we provide a more detailed characterization of the limit cycle oscillators (LCOs) with the intent of resolving possible asymmetries. Secondly, we use sensory information from a biped robot's "limbs" to set the appropriate timing for the discrete pulse to correct the asymmetries, making it possible to take the computer out of the loop in the generation of the stimulus. Eventually, we believe this approach could lead to development of a neuroprosthetic device for restoring locomotion after paralysis or amputation.

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

A mixed-signal very large scale integration (VLSI) chip for large scale emulation of spiking neural networks is presented. The chip contains 2400 silicon neurons with fully programmable and reconfigurable synaptic connectivity. Each neuron implements a discrete-time model of a single-compartment cell. The model allows for analog membrane dynamics and an arbitrary number of synaptic connections, each with tunable conductance and reversal potential. The array of silicon neurons functions as an address-event (AE) transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven digital bus. Address encoding and conflict resolution of spiking events are implemented via a randomized arbitration scheme that ensures balanced servicing of event requests across the array. Routing of events is implemented externally using dynamically programmable random-access memory that stores a postsynaptic address, the conductance, and the reversal potential of each synaptic connection. Here, we describe the silicon neuron circuits, present experimental data characterizing the 3 mm x 3 mm chip fabricated in 0.5-microm complementary metal-oxide-semiconductor (CMOS) technology, and demonstrate its utility by configuring the hardware to emulate a model of attractor dynamics and waves of neural activity during sleep in rat hippocampus.

A new central pattern generator chip with 24 silicon neurons and reprogrammable connectivity is presented. The 3mm /spl times/ 3mm chip fabricated in a 3M2P 0.5/spl mu/m process contains 1032 synapses, each with multiple floating gates for storing parameters governing synaptic strength and polarity. Every neuron includes a dendritic compartment with 12 externally-addressable synaptic inputs and 24 recurrent synaptic inputs, enabling construction of a fully-interconnected network with sensory feedback from off-chip elements. In addition to describing the chip architecture and neuron circuits, preliminary results from single oscillating neurons and pairs of phase-locked neurons are shown. This work represents the realization of a design presented at ISCAS'05, and an improvement over our 2nd generation CPG chip presented at ISCAS'04.

We show that an ongoing locomotor pattern can be modulated by application of discrete electrical stimuli to the spinal cord at specific phases of the locomotor cycle. Data is presented from a series of experiments on in vitro lamprey spinal cords, which were used as an animal model for severe spinal cord injury. For any given stimulus, the effects on frequency, length, and symmetry of locomotor output show a strong dependence on the phase at which stimulation is applied. The most significant changes are seen when stimulation occurs during motor bursting: stimuli applied to the ipsilateral spinal hemicord increase the burst length, while stimuli applied to the contralateral spinal hemicord decrease the burst length. Simulations using experimentally-measured phase-dependent responses indicate that by monitoring the state of the neural system, it should be possible to apply stimuli at the appropriate times to modulate the lamprey "gait" on a cycle-by-cycle basis. Eventually, this approach could lead to development of a neuroprosthetic device for restoring locomotion after paralysis.

We have constructed a system that uses an array of 9,600 spiking sili- con neurons, a fast microcontroller, and digital memory, to implement a reconfigurable network of integrate-and-fire neurons. The system is designed for rapid prototyping of spiking neural networks that require high-throughput communication with external address-event hardware. Arbitrary network topologies can be implemented by selectively rout- ing address-events to specific internal or external targets according to a memory-based projective field mapping. The utility and versatility of the system is demonstrated by configuring it as a three-stage network that accepts input from an address-event imager, detects salient regions of the image, and performs spatial acuity modulation around a high-resolution fovea that is centered on the location of highest salience.

Address-event representation (AER), originally proposed as a means to communicate sparse neural events between neuromorphic chips, has proven efficient in implementing large-scale networks with arbitrary, configurable synaptic connectivity. In this work, we further extend the functionality of AER to implement arbitrary, configurable synaptic plas- ticity in the address domain. As proof of concept, we implement a bi- ologically inspired form of spike timing-dependent plasticity (STDP) based on relative timing of events in an AER framework. Experimen- tal results from an analog VLSI integrate-and-fire network demonstrate address domain learning in a task that requires neurons to group corre- lated inputs.