This article presents the conception, design, and realization of a fully differential two-stage CMOS amplifier, that is, unconditionally stable for any value of the capacitive load. This is simply achieved by sending a scaled replica of the output stage current to the amplifier virtual ground in order to create a left half-plane (LHP) zero in the loop gain that either cancels or tracks the output pole in all process, voltage, and temperature (PVT) conditions. Consequently, from a stability point of view, the amplifier behavior resembles that of a single-pole OTA. Starting from an existing two-stage gain-programmable amplifier, designed in a 0.18-$\mu $m bipolar-CMOS-DMOS (BCD) process that was able to drive only 10 pF without encountering into stability issues, a simple circuit has been added to extend the stability to any capacitive load value. An interesting and unusual method, based on the frequency behavior of the unloaded closed-loop amplifier output impedance, has been introduced to further verify the unconditional stability of this solution. Measurements show a high degree of stability in any load conditions. In the used 0.18-$\mu $m BCD technology, silicon area and current consumption of the extra circuit are only 0.0004 mm2 and$2~\mu $A, respectively, with a 5-V power supply.

This paper presents the conception, design and realization of a fully-differential two-stage CMOS amplifier that is unconditionally stable for any value of the capacitive load. This is simply achieved by sending a scaled replica of the output stage current to the amplifier virtual ground such as to create a Left Half-Plane (LHP) zero in the loop-gain that either cancels or tracks the output pole in all process, voltage, and temperature (PVT) conditions. Consequently, from a stability point of view the amplifier behavior resembles that of a single-pole OTA. Starting from an existing two-stage gain-programmable amplifier, designed in a 0.18μm Bipolar-CMOS-DMOS (BCD) process, that was able to drive only 10pF without incurring into stability issues, a simple circuit has been added to extend the stability to any capacitive load value. Measurements, given with loads ranging from 0pF to 100nF, show high degree of stability in any load conditions. In the used 0.18μm BCD technology, silicon area and current consumption of the extra circuit are only 0.0004mm2and 2μA, respectively, with a 5 V power supply.

The paper regards a new active resistor for ultra-low power applications. Thanks to the chosen topology, based on feedback and operational amplifier, it allows to accurately emulate the voltage versus current characteristic (V-I) of a component with respect to the process, temperature and power supply variations. Furthermore, using a transistor in a series configuration as reference, it is possible to obtain very high resistance values with up to 10 times less area with respect to the resistors available in standard complementary metal-oxide-semiconductor (CMOS) technology. The circuit has been simulated using 1.2-V transistors of a 130nm CMOS technology. Compared with a standard p+ poly-silicon resistors, it exhibits equivalent performance parameters using less area.

In this paper a low-power and high-performance 2nd-order complex band-pass filter in trans-impedance amplifier (TIA) configuration is presented. Thanks to the adopted topology for the passive network and active-components exceeds current solutions exhibiting a gain as high as 121.5 dB$_\Omega $and 1.57 MHz of bandwidth centered around 1.33 MHz. The output noise is only 630 nV/${\sqrt {Hz}}$. Furthermore, a new fully-differential class-AB operational trans-conductance amplifier (OTA) provides the required current to drive heavy ADC loads with very fast signals while an improved common-mode feedback circuit enables ultra low current without introducing stability and avoids start-up problems. The filter has been integrated in a 90-nm complementary metal oxide semiconductor (CMOS) technology. Despite the high performance and accuracy of the transfer function the power consumption is only$400~\mu \text{A}$from a 1.2-V power supply.

A low-power low-area CMOS algorithmic A/D converter that does not require trimming nor digital calibration is presented. The topology is based on a classical cyclic A/D conversion using a capacitor ratio-independent computation circuitry. All the nonidealities have been carefully analyzed and reduced by proper choices of design and layout solutions. As a result the errors coming from opamp offset and finite open-loop dc gain, switch charge injection and clock feedthrough, parasitic capacitors, and intrinsic noise sources are reduced under the LSB level. To process a multiplexed (8 channels) single-ended analogue input, an efficient single-ended to fully differential circuit has been presented. The converter achieves 11 bit accuracy in the Nyquist band at a sampling rate of 8kSps. The total power dissipation is only 350/spl mu/W at 2.7V supply voltage. The active area is 0.3 mm/sup 2/ in a 0.35 /spl mu/m 5 metal levels CMOS technology with double-poly linear capacitors.

This paper discusses manufacturabilty of state-of-the-art low power technologies.We report the results on two generations of bulk CMOS technologies, triple-well CMOS and Thin Film Silicon on Insulator (TFSOI) technologies.We present technology capabilities for several values of supply voltage and address the issue of performance scaling with the supply voltage reduction.Then we focus on the statistical characterization of these technologies and discuss both interchip and intrachip variations.Finally, we present the digital and analog designer perspectives on the low power IC operation.