Bagging forms a committee of classifiers by bootstrap aggregation of training sets from a pool of training data. A simple alternative to bagging is to partition the data into disjoint subsets. Experiments on various datasets show that, given the same size partitions and bags, disjoint partitions result in better performance than bootstrap aggregates (bags). Many applications (e.g., protein structure prediction) involve the use of datasets that are too large to handle in the memory of a typical computer. Our results indicate that, in such applications, the simple approach of creating a committee of classifiers from disjoint partitions is preferred over the more complex approach of bagging.

Fixed rate, variable rate, and feed forward pointer spreading as well as stuff threshold modulation (STM) are analyzed as methods for reducing jitter caused by SONET pointer adjustments. Each method of jitter reduction is described, theoretical analysis is developed to predict RMS jitter performance, and simulation results are presented to illustrate RMS and peak-to-peak jitter performance. A new method of implementing feed forward pointer spreading is described in which STM is used to transmit the synchronizer elastic store phase information.>

The authors have designed and characterized a single-error-correcting (SEC), double-error-detecting (DED) code applicable to the STS-1 SONET format. They show that if two of the presently unallocated bytes in the path overhead field of STS-1 are assigned for error-correction coding (ECC), a (6208, 6195) shortened extended Hamming code can be implemented using as few as 660 gates plus a 1-kbyte RAM IC, achieving (O8.6*10/sup -3/ P/sub 2//sup 2/) BER reduction with 139 mu s of signal delay. The authors explain how the existing BIP-8 error-monitoring byte of the STS-1 format could be integrated with the proposed ECC so that a net allocation of only one new STS-1 overhead byte is required for both error monitoring and error correction. The implementation method is such that all path, line, and section overhead functions in SONET can be performed at intermediate sites without requiring ECC decoding. The authors consider application alternatives and describe the forward-error-correction (FEC) circuit design and trial results. System issues are covered, including network delay, effects of error extension on BER, addition of double-error detection, performance monitoring, and options for intelligent network control and management of FEC functions. Codes related to their path-level design that are applicable to a number of other strategies for applying FEC in SONET are presented.>

A technique for precise synchronization of the time-of-day clocks in networks of digital cross-connect systems (DCSs) is described. This method is intended to enhance the performance of reconfigurable transport networks and is specifically devised to exploit the fine time resolution of the carrier signals to which a DCS has direct access. The resulting scheme is a master-slave, multisite, implicitly delay compensated, nonhierarchical time-transfer method with a theoretical precision of one bit time at the carrier rate. In practice, precision is limited by transmission span delay asymmetries but residual time errors of under 1 mu s are predicted. The method is intended for n/n space-switching DCS, but other DCS properties can be accommodated. Requirements for DCS equipment design are given, including a generic circuit module for DCS hardware support of the time transfer function. The proposed method applies to DS-3 networks or synchronous optical networks and requires no change in the standards. Measurement or improved estimation of characteristic span delay asymmetries is recommended to refine the preliminary performance estimate.>