As the CMOS process scales down, digital circuits become more susceptible to hold time violations due to increased sensitivity to supply voltage fluctuations. Since hold time violation is fatal, sufficient hold fixing buffers need to be inserted into the short paths to prevent it. However, by assuming a constant power supply level, traditional hold fixing causes imprecise and overly conservative timing analysis and hence leads to circuit overhead and degraded performance. To address this, we propose a power supply noise (PSN)-aware dynamic timing analysis for realistic hold time analysis and efficient hold buffer optimization, which integrates a machine learning-based timing model into the conventional design flow. Building on the highly effective application of the Weibull cumulative distribution function and machine learning for dynamic PSN-aware timing analysis, we propose introducing an additional parameter for PSN amplitude, which has a significant impact on delay, and narrowing the overall parameter range using real PSN waveforms extracted from the RedHawk. This approach achieves a prediction error of only 3.45% for cell delay and 5.1 % for path delay, while also reducing dataset acquisition costs. To the best of our knowledge, this work is the first to apply PSN-aware dynamic timing analysis specifically for hold optimization, mitigating the pessimism of traditional static timing analysis (STA) and effectively minimizing redundant hold fixing buffers while remaining compatible with existing design workflows. Since short paths often overlap with critical paths, reducing redundant hold buffers not only decreases area overhead but also enhances performance. Applied to a 22 nm, 64-point Fast Fourier Transform (FFT) circuit, our EDA compatible method combined with a greedy algorithm reduces hold buffers by 55%, achieving not only 6.79%circuit area reduction but also 8.1 % performance improvement due to the elimination of redundant buffers in short and critical paths.

The on-chip droop in processor may cause a severe voltage reduction resulting in a need for high-speed and high-resolution on-chip voltage sensors. However, traditional voltage sensors hardly achieve high resolution at GHz-level sampling rate and require multiple cycles to obtain quantized results. Therefore, we propose an on-chip all-digital voltage sensor with dynamic PVT calibration for droop detection and a unified voltage monitor and scaling (UVMS) systems for efficiency improvement. We propose a balanced ring oscillator for high resolution and Nyquist counter-based encoder for GHz-level sampling. A light-weight dynamic PVT calibration using temperature sensor is proposed to resist the PVT variations and nonlinearity. Then, an adaptive prediction mechanism is proposed for 0-latency voltage detection. Fabricated in a 28nm CMOS technology, our voltage sensor achieves a high resolution of 7.32 mV/LSB at a 2 GS/s or 1.92 mV/LSB at a 0.5 GS/s sample rate with 0-latency and a calibration error of only 1 LSB. Implemented in a BNN accelerator, proposed UVMS compresses the margin and achieves a power gain of 37% - 57% at frequencies ranging from 31 MHz to 337 MHz.