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Son Dao Trong

dblp:29/6737 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 2 · 1 first-authorSystems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Processor architecture and microarchitecture · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › computer arithmetic
floating-point arithmetic
0.112005
FPU Implementations with Denormalized Numbers · IEEE Trans. Computers 2005
Integrated circuit design › digital arithmetic circuits
floating-point unit design
0.112005
FPU Implementations with Denormalized Numbers · IEEE Trans. Computers 2005

Methods — techniques the papers use, named apart from their topics

hardware trap handling · 0.1
YearPublicationVenuePosition
2007 P6 Binary Floating-Point Unit
abstract
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a technology independent measure. For most dependent instructions, its fused multiply-add dataflow has only 6 effective pipeline stages. This is nearly equivalent to its predecessor, the Power 5, even though its technology independent frequency has increased over 70%. Overall the frequency has improved over 100%. It achieves this high performance through aggressive feedback paths, circuit design and layout. The pipeline has 7 stages but data may be fed back to dependent operations prior to rounding and complete normalization. Division and square root algorithms are also described which take advantage of high-precision linear approximation hardware for obtaining a reciprocal or reciprocal square root approximation.
Son Dao Trong, Martin S. Schmookler, Eric M. Schwarz, Michael Kroener
IEEE Symposium on Computer Arithmetic1
2005 FPU Implementations with Denormalized Numbers
abstract
Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that certain designs have elected to handle them in software rather than in hardware. Traps to software can result in long execution times, which renders denormalized numbers useless to programmers. This does not have to happen. With a small amount of additional hardware, denormalized numbers and underflows can be handled close to the speed of normalized numbers. This paper summarizes the little known techniques for handling denormalized numbers. Most of the techniques described here only appear in filed or pending patent applications.
Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong
IEEE Trans. Computers3
2003 Hardware Implementations of Denormalized Numbers
abstract
Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that some designs have elected to handle them in software rather than hardware. This has resulted in execution times in the tens of thousands of cycles, which has made denormalized numbers useless to programmers. This does not have to happen. With a small amount of additional hardware, denormalized numbers and underflows can be handled close to the speed of normalized numbers. We will summarize the little known techniques for handling denormalized numbers. Most of the techniques discussed have only been discussed in filed or pending patent applications.
Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong
IEEE Symposium on Computer Arithmetic3