Autonomous driving technologies are rapidly advancing, driven by the need for safer, more efficient, and intelligent transportation systems. A fundamental component of these systems is the perception module, which enables vehicles to understand and react to their surrounding environment. Object detection, in particular, is essential for identifying dynamic and static elements on the road, such as pedestrians, vehicles, traffic signs, and obstacles. In this work, we explore and enhance the capabilities of state-of-the-art deep learning-based object detectors within the YOLO (You Only Look Once) family, focusing on the latest versions: YOLOv10 and YOLOv11. We fine-tuned and optimized multiple variants of each model—namely, nano (n), small (s), medium (m), and large (l)—to improve detection accuracy and computational efficiency for real-time autonomous driving applications. The models were trained and evaluated on a diverse road object, and performance was measured using key metrics including precision, mean Average Precision (mAP), and Precision-Recall curves. Experimental results reveal that the fine-tuned YOLOv10n achieved a peak class-level precision of 1.00 at a specific confidence threshold (0.997), indicating that perfect precision was observed for certain classes under high-confidence conditions, while the overall mean precision and mAP metrics reflect more balanced model performance, while YOLOv11s attained the best result within its group with a precision of 0.91 at a threshold of 0.972. These findings demonstrate the potential of tailored YOLO architectures to meet the demanding requirements of real-world autonomous navigation systems.

Fifth generation and beyond networks are envisioned to support multi industrial Internet of Things (IIoT) applications with a diverse quality-of-service (QoS) requirements. Network slicing is recognized as a flagship technology that enables IIoT networks with multiservices and resource requirements by allowing the network-as-infrastructure transition to the network-as-service. Motivated by the increasing IIoT computational capacity, and taking into consideration the QoS satisfaction and private data sharing challenges, federated reinforcement learning (RL) has become a promising approach that distributes data acquisition and computation tasks over distributed network agents, exploiting local computation capacities and agent's self-learning experiences. This article proposes a novel deep RL scheme to provide a federated and dynamic network management and resource allocation for differentiated QoS services in future IIoT networks. This involves IIoT slices resource allocation in terms of transmission power (TP) and spreading factor (SF) according to the slices QoS requirements. Toward this goal, the proposed deep federated Q-learning (DFQL) is reached into two main steps. First, we propose a multiagent deep Q-learning-based dynamic slices TP and SF adjustment process that aims at maximizing self-QoS requirements in term of throughput and delay. Second, the deep federated learning is proposed to learn multiagent self-model and enable them to find an optimal action decision on the TP and the SF that satisfy IIoT virtual network slice QoS reward, exploiting the shared experiences between agents. Simulation results show that the proposed DFQL framework achieves efficient performance compared to the traditional approaches.

Computation of stereoscopic depth and disparity map extraction are dynamic research topics. A large variety of algorithms has been developed, among which we cite feature matching, moment extraction, and image representation using descriptors to determine a disparity map. This paper proposes a new method for stereo matching based on Fourier descriptors. The robustness of these descriptors under photometric and geometric transformations provides a better representation of a template or a local region in the image. In our work, we specifically use generalized Fourier descriptors to compute a robust cost function. Then, a box filter is applied for cost aggregation to enforce a smoothness constraint between neighboring pixels. Optimization and disparity calculation are done using dynamic programming, with a cost based on similarity between generalized Fourier descriptors using Euclidean distance. This local cost function is used to optimize correspondences. Our stereo matching algorithm is evaluated using the Middlebury stereo benchmark; our approach has been implemented on parallel high-performance graphics hardware using CUDA to accelerate our algorithm, giving a real-time implementation.

The new High‐Efficiency Video Coding (HEVC) standard doubles the video compression ratio compared to the previous H.264/AVC at the same video quality and without any degradation. However, this important performance is achieved by increasing the encoder computational complexity. That's why HEVC complexity is a crucial subject. The most time consuming and the most intensive computing part of HEVC is the motion estimation based principally on the sum of absolute differences (SAD) or the sum of square differences (SSD) algorithms. For these reasons, the authors proposed an implementation of these algorithms on a low cost NVIDIA GPU (graphics processing unit) using the Fermi architecture developed with Compute Unified Device Architecture language. The proposed algorithm is based on the parallel‐difference and the parallel‐reduction process. The investigational results show a significant speed‐up in terms of execution time for most 64 × 64 pixel blocks. In fact, the proposed parallel algorithm permits a significant reduction in the execution time that reaches up to 56.17 and 30.4%, compared to the CPU, for SAD and SSD algorithms, respectively. This improvement proves that parallelising the algorithm with the new proposed reduction process for the Fermi‐GPU generation leads to better results. These findings are based on a static study that determines the PU percentage utilisation for each dimension in the HEVC. This study shows that the larger PUs are the most utilised in temporal levels 3 and 4, which attain 84.56% for class E. This improvement is accompanied by an average peak signal‐to‐noise ratio loss of 0.095 dB and a decrease of 0.64% in terms of BitRate.

A fundamental problem in designing sensors network is locating their position. The data collected from the sensors can be used to detect, track and organize objects of interest. In this paper, we present and evaluate an improvement of the famous DV-HOP algorithm in order to increase the localization accuracy and reduce energy consumption. The benefits of the suggested algorithm are twofold. First, it uses a new technique for solving an N-equation system and a weighted least squares method (WLS) to minimize the error of the expected distance between anchor and unknown nodes. Second, this method uses the hop-size average of the anchor node, which is computed by unknown nodes, to reduce the overall communication cost between nodes. This yields a significant reduction in both energy consumption and execution time. The performance of our proposed approach was evaluated and compared to other classical algorithms. Results show that significant enhancement is achieved within the proposed algorithm when measuring different metrics such as energy, execution time and localization error while varying simulation parameters such as the total number of nodes, percentage of anchor node and communication range.

The Graphics processors or GPUs have become in a few years powerful tools for applications that require a massively parallel computing. Currently include the applications in multimedia processing, the engineering science and image processing in real time. They offer many advantages such as acceleration of treatment and down energy consumption from an equivalent CPU power. In this paper, we will show the effectiveness of our approach sobel filter (features extraction) by parallelizing the processing applied to different images with different sizes.

The research in the domain of image compression increased significantly where the requirements of transmission images have raised enormously. Image compression is very important in digital image processing. It plays a crucial role in efficient transmission and storage of images. The most widely used method of lossy compression is JPEG standard. In this paper, we will discuss the implementation of JPEG encoder for Field-Programmable Gate Array (FPGA). The target device is Virtex V ML507. The JPEG encoder was synthesized with EDK designs at the clock frequency of 125 MHz. The implementation starts with the standard JPEG algorithm that is analyzed to extract the interesting functions that can be implemented in an FPGA: quantization, Discrete Cosine Transform (D C T) and Huffman coding. Once identified, these functions are implemented in software. The design can compress from a BMP to a JPEG image with displaying the compressed one on screen.

In this paper, a fast configuration for Motion Estimation (ME) is described in order to reduce the computational time of the new High Efficient Video Coding (HEVC). This configuration uses the Coded Block Flag (CBF) Fast Method (CFM), the Early Coding Unit (CU) termination (ECU) and the Early Skip Detection (ESD) modes. The Diamond Pattern is used as a search algorithm for ME in the encoding process. Compared to the latest original reference software test model (HM) 16.2 of the HEVC, experimental results had showed that the complexity is reduced, in average, by 56.75% with a small bit-rate and PSNR degradation.

Because of the increasing number of population of vehicles, the road traffic accidents are becoming more and more serious in recent years. Hence, improving driver assistance systems for security has become an important area of research. This paper presents a robust lane detection and tracking system based on monocular vision. We use the Lane Departure Warning (LDW) systems to detect the position of the vehicle with respect to the lane boundary. An algorithm to detect the road lane marking and to control the direction of the vehicle is proposed. Our work consists in establishing a Region Of Interest (ROI) of the road images, data pre-processing using the Gaussian filter and then apply the Canny edge detector to enhance lane boundaries. A method to extract lane boundaries based on color information and image segmentation by using the histogram threshold, Hough transform is proposed, and the current vehicle position is obtained. In such a case, we can decide if the vehicle is doing lane departure used on the vehicle's position, the system sends a warning message to the driver. Our proposed algorithm works accurately with various lighting conditions as well as on different road types.

JPEG 2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG 2000 standard has not only better compression ratios, but it also offers some exciting features. As it's hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. In this paper we proposed an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm. The proposed design is implemented on an FPGA platform. EBCOT is very important in the compression process of the JPEG 2000 standard. The proposed architecture is on four coding operations which are pipelined. The proposed architecture is implemented in a causal mode.

JPEG is the most commonly used image compression standard in today's world. Researchers have found that JPEG has many limitations, in order to overcome all those limitations and to add on new improved features, ISO and ITU-T have come up with new image compression standard, which is JPEG2000. The JPEG2000 is intended to provide a new image coding/decoding system using state of the art compression techniques, based on the use of two important parts coding/decoding processes which are Wavelet Transform and Arithmetic Coding. As it's hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. The embedded block coding with optimized truncation (EBCOT) algorithm is the heart of the JPEG 2000 image compression system. Context Based Adaptive Arithmetic coding is used and the MQ coder is adopted in the JPEG2000. In this paper we propose efficient faster architecture for the JPEG2000 MQ-Coder which is implemented in VHDL hardware description language and synthesized using Xilinx's design flows ISE 13.1. The implementation results show that the design operates at 354.937 MHz when implemented on Virtex-6. Post synthesis simulations indicate that the proposed architecture is able to compress 35 video frames/s of high definition TV of 1920p.

Detecting pedestrians is a challenging problem owing to the motion of the subjects, the camera and the background and to variations in pose, appearance, clothing, illumination and background clutter. The Region Covariance Matrix (RCM) descriptors show experimentally significantly out-performs existing feature sets for pedestrian detection. In this paper, we present an efficient features extraction scheme: the Integral CovReg, inspired from Region Covariance Matrix (RCM) descriptors, combined with SVM classifier for pedestrian detection.

In this paper, we propose a wormhole router architecture for symmetric 3D-mesh Networks-on-Chip (NoCs) with virtual channels. It uses the credit-based flow control mechanism and dimension-order routing XYZ algorithm. With priority-based scheduling, our 3D on-chip communication model can support the management of different levels of quality-of-service. The router is implemented on FPGA device using the Xilinx ISE software. Various designs were synthesized to verify the capability of our router. From the implementation results, the proposed router architecture enables a higher data rate and low latency at a reasonable power and area overheads. Furthermore, we demonstrate an analysis and comparison of the cost and performance results between the 2D and 3D designs.