High energy efficiency and high-capacity embedded SRAMs are essential for data-centric applications. CFET technology offers a scalable solution to reduce the SRAM cell area. However, the optimal routing of signal and power wires in CFET SRAM to achieve better performance remains unresolved. This study proposes a Design Technology Co-Optimization (DTCO) framework for CFET SRAM cells. After generating 3D cell structures through layouts, parasitic resistance, and capacitance are analyzed for 6T and 8T SRAM arrays. Compared to CFET SRAM using single-sided signal routing with backside power delivery network (BS-PDN), CFET SRAM with double-sided signal/power routing, which efficiently leverages the space above and below the CFET SRAM cells, exhibits reduced parasitic capacitance. This reduction significantly improves read delay, write delay, read power, and write power for both 6T and 8T SRAMs, making it a promising option for high-throughput data-centric applications.

This paper provides an in-depth exploration of an RF device technology developed on the nanosheet FET (NSFET) platform. A buried power rail (BPR) RF device layout delivers an impressive cut-off frequency (Ft) / maximum oscillation frequency (Fmax) ratio of 535/610 GHz. Moreover, when optimizing the BPR structure and combining it with the Contact over Active-Gate (COAG) structure, remarkable results are achieved, with Ft/Fmax reaching 532/699 GHz. Notably, this proposed COAG mix BPR design effectively reduces gate resistance while improving Fmax by approximately 50% compared to the baseline structure, all while maintaining performance levels equal to the latter.

Continued scaling of the interconnect geometry increases the metal resistance which degrades the performance of SRAM in advanced technology nodes. We propose an energy-efficient multi-tiers monolithic 3D (M3D) SRAM cell design with stacked 2D material nanosheet FETs to release the impact of metal line resistance. Considering the 2nm node design rules, the 3-tier M3D SRAM cell with stacked MoS2 FETs shows a 42% reduction in cell area, 49% improvement in read access time, and 68% improvement in energy-delay product. The energy- and area-efficient high-performance 3- tier M3D SRAM cell enables intelligent functionalities for the area and energy-constrained edge computing devices.

In this work, we investigate the energy efficiency and memory window of split-gate ferroelectric FET (SG-FeFET) non-volatile memory (NVM) compared with the single gate ferroelectric FET (FeFET) NVM. A novel sequential write scheme is proposed to improve the read distinguishability (IR1/IR0), memory window (MW), and energy efficiency of SG-FeFET NVM. Sufficient MW is essential to meet the retention and endurance requirements of ferroelectric oxide based NVM. The impact of gate length (LG) on the MW and IR1/IR0of SG-FeFET and FeFET with MFMIS structure is analyzed. Our results show that with fixed MW, FeFET with longer LG(= 190 nm) requires 2.5 V write voltage (Vwrite); while FeFET with shorter LG(= 50 nm) decreases the Vwrite to 2 V. Our proposed SG-FeFET NVM (LG= 50 nm) with sequential write scheme can further reduce the Vwrite to 1.85 V, and improve the write energy by 21%. SG-FeFET NVM with improved energy efficiency is beneficial for hardware implementations of deep neural networks (DNNs) for low power AI and IoT applications.

In this work, we compare the read stability and writability between 6T negative capacitance FinFET (NC-FinFET) SRAM cell and the baseline 6T FinFET SRAM cell in the subthreshold and superthreshold operations. In the subthreshold operation (VDD= 0.4V), NC-FinFET SRAM cell shows better read, write, and hold static noise margins than FinFET SRAM cell. During read operation at VDD= 0.4V, pass-gate (PG) NC-FinFET becomes weaker due to the negative differential resistance (NDR) in the saturation region, which reduces the read disturb voltage of NC-FinFET SRAM cell. During write operation at VDD= 0.4V, PG NC-FinFET with internal voltage amplification becomes stronger in the linear region, and pull-up NC-FinFET with NDR effect becomes weaker in the saturation region, which improves the writability of NC-FinFET SRAM cell. In other words, negative capacitance effect resolves the conflict between read stability and writability for subthreshold operation. For the superthreshold operation (VDD= 1V), NC-FinFET SRAM cell still exhibits 1.73 times larger RSNM (= 183mV) than FinFET SRAM cell, and adequate WSNM (= 198mV). 6T NC-FinFET SRAM cell performs superior stability for both subthreshold and superthreshold operations.

This paper investigates the impacts of negative and positive bias temperature instabilities (NBTI and PBTI) on the stability and performance of ultra-thin-body (UTB) GeOI 6T SRAM cells integrated in monolithic 3D scheme with interlayer coupling. Various bitcell layouts with different gate alignments of transistors from distinct layers are investigated. The worst case stress scenarios for read and write operations are analyzed. The optimized monolithic 3D UTB GeOI SRAM with the pulldown NFET tier stacked over the pull-up PFET tier and under forward PFET back-gate bias shows improvements in read stability and cell read-access time compared with the 2D UTB GeOI SRAM. Monolithic 3D UTB GeOI SRAM with high threshold voltage (Vth) design can enhance the improvements in stability and performance over 2D SRAM. Moreover, the optimized monolithic 3D UTB GeOI SRAM can mitigate the temporal degradations in stability and performance due to BTI stress because the BTI induced Vth degradations can be suppressed by interlayer coupling in monolithic 3D scheme.

In this paper, we comprehensively investigate the impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-look-ahead adder (CLA) circuits operating in near-threshold region using atomistic 3D TCAD mixed-mode simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that at low operating voltage (onand Cg, aveand their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioffvariability of TFET devices.

This paper investigates the impacts of Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) on the stability and performance of Ultra-Thin-Body (UTB) GeOI 6T SRAM cells compared with the SOI counterparts. Worst case stress scenarios for Read and Write operations are analyzed. For UTB GeOI SRAM cells, PBTI dominates the degradations in RSNM, HSNM, cell Read access time, and Time-to-Write, while for UTB SOI SRAM cells, NBTI dominates the degradations in RSNM, HSNM, and Time-to-Write. WSNM only slightly degrades due to NBTI/PBTI. Threshold voltage design and Word-Line Under-Drive (WLUD) Read-Assist techniques are analyzed to compensate the stability degradation due to NBTI/PBTI for UTB GeOI SRAM cells. Compared with the nominal UTB GeOI SRAM cells with low Vth design, UTB GeOI SRAM cells with high Vth design suffer less NBTI/PBTI degradations and exhibit significant improvement in RSNM and HSNM, and comparable performance compared with the nominal UTB SOI SRAM cells.

In this work, we comprehensively investigate the impact of interlayer coupling on monolithic 3D logic circuits and 6T SRAM cells using TCAD mixed-mode simulations. In addition to reduced interconnection length, monolithic 3D integration enables further performance enhancements with optimal layout. Our study indicates that minimum leakage, equivalent to the planar 2D circuits with dual reverse body biases, is achievable for circuits stacked in 3D fashion. Moreover, stacking NFET layer over the PFET tier facilitates larger design margins for SRAM cell stability and performance.

This paper evaluates the impacts of Read- and Write-Assist circuits on the GeOI FinFET 6T SRAM cells compared with the SOI counterparts. The Word-Line Under-Drive (WLUD) Read-Assist is more efficient to improve the Read Static Noise Margin (RSNM) and Read VMIN of FNSP GeOI FinFET SRAM cells compared with the SOI counterparts. GeOI FinFET SRAM cells with WLUD show smaller cell Read access-time compared with the SOI FinFET SRAM cells at both 25°C and 125 °C. Negative Bit-Line (NBL) Write-Assist is more efficient to improve the Write Static Noise Margin (WSNM) than VCS (cell supply) lowering for both GeOI and SOI FinFET SRAM cells. NBL Write-Assist shows larger WSNM improvement for GeOI FinFET SRAM cells than the SOI counterparts at 125°C.

In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, Vmin and performance. The proposed cell is evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation.

In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM atVCS= 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (Leff, EOT,Wfin, andHfin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of μ/σ ratio.

This paper analyzes the stability, margin, and performance of Ultra-Thin-Body (UTB) SOI 6T/8T SRAM cells operating in subthreshold region. An analytical SNM model for UTB SOI 6T/8T SRAM cells operating in the subthreshold region is presented to investigate the Read SNM (RSNM) and Write SNM (WSNM). Our results indicate that back-gating technique is more effective in the subthreshold region than in the superthreshold region for improving RSNM and WSNM. The UTB SOI 6T SRAM cell with back-gating technique to increase the strength of the pull-up transistors and decrease the strength of the pass-gate transistors shows comparable RSNM in the subthreshold region with the 10T bulk subthreshold SRAM cell and an improvement in RSNM variation. Due to better electrostatic integrity, back-gating technique (pull-up PFET with positive back-gate bias, pull-down/pass-gate NFET's with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell β-ratio shows limited improvement on RSNM and has no benefit on SNM variability for subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2X larger than the 6T SRAM cell in the subthreshold region. Mixed-mode device/circuit simulations show that 6T/8T UTB SOI SRAMs operating in the subthreshold region can meet/support the stability, leakage/density, and frequency requirements for intended application space of subthreshold SRAMs.